Commit 2643f0b0 authored by Bjorn Andersson's avatar Bjorn Andersson
Browse files

Merge branch '20230909123431.1725728-1-quic_ajipan@quicinc.com' into clk-for-6.7 

Merge the SM4450 RPMHCC and GCC through a topic branch, to allow reuse
of the defines from the DeviceTree binding in the DeviceTree source.
parents 471e2875 c32c4ef9

Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ properties: 
      - qcom,sdx55-rpmh-clk

      - qcom,sdx65-rpmh-clk

      - qcom,sdx75-rpmh-clk

      - qcom,sm4450-rpmh-clk

      - qcom,sm6350-rpmh-clk

      - qcom,sm8150-rpmh-clk

      - qcom,sm8250-rpmh-clk

Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml

0 → 100644
+55 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,sm4450-gcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller on SM4450



maintainers:

  - Ajit Pandey <quic_ajipan@quicinc.com>

  - Taniya Das <quic_tdas@quicinc.com>



description: |

  Qualcomm global clock control module provides the clocks, resets and power

  domains on SM4450



  See also:: include/dt-bindings/clock/qcom,sm4450-gcc.h



properties:

  compatible:

    const: qcom,sm4450-gcc



  clocks:

    items:

      - description: Board XO source

      - description: Sleep clock source

      - description: UFS Phy Rx symbol 0 clock source

      - description: UFS Phy Rx symbol 1 clock source

      - description: UFS Phy Tx symbol 0 clock source

      - description: USB3 Phy wrapper pipe clock source



required:

  - compatible

  - clocks



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

      compatible = "qcom,sm4450-gcc";

      reg = <0x00100000 0x001f4200>;

      clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,

               <&ufs_mem_phy 0>, <&ufs_mem_phy 1>,

               <&ufs_mem_phy 2>, <&usb_1_qmpphy>;

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };



...

drivers/clk/qcom/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -841,6 +841,15 @@ config SM_DISPCC_8550 
	  Say Y if you want to support display devices and functionality such as

	  splash screen.



config SM_GCC_4450

	tristate "SM4450 Global Clock Controller"

	depends on ARM64 || COMPILE_TEST

	select QCOM_GDSC

	help

	  Support for the global clock controller on SM4450 devices.

	  Say Y if you want to use peripheral devices such as UART, SPI,

	  I2C, USB, SD/UFS, PCIe, etc.



config SM_GCC_6115

	tristate "SM6115 and SM4250 Global Clock Controller"

	depends on ARM64 || COMPILE_TEST

drivers/clk/qcom/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -110,6 +110,7 @@ obj-$(CONFIG_SM_DISPCC_6375) += dispcc-sm6375.o 
obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o

obj-$(CONFIG_SM_DISPCC_8450) += dispcc-sm8450.o

obj-$(CONFIG_SM_DISPCC_8550) += dispcc-sm8550.o

obj-$(CONFIG_SM_GCC_4450) += gcc-sm4450.o

obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o

obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o

obj-$(CONFIG_SM_GCC_6350) += gcc-sm6350.o

drivers/clk/qcom/clk-rpmh.c

+21 −0
Original line number Diff line number Diff line
@@ -350,6 +350,7 @@ DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2); 


DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a4, "lnbclka1", 4);

DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a4, "lnbclka2", 4);

DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a4, "lnbclka3", 4);



DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _g4, "lnbclkg2", 4);

DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _g4, "lnbclkg3", 4);
@@ -717,6 +718,25 @@ static const struct clk_rpmh_desc clk_rpmh_sdx75 = { 
	.num_clks = ARRAY_SIZE(sdx75_rpmh_clocks),

};



static struct clk_hw *sm4450_rpmh_clocks[] = {

	[RPMH_CXO_CLK]		= &clk_rpmh_bi_tcxo_div4.hw,

	[RPMH_CXO_CLK_A]	= &clk_rpmh_bi_tcxo_div4_ao.hw,

	[RPMH_LN_BB_CLK2]	= &clk_rpmh_ln_bb_clk2_a4.hw,

	[RPMH_LN_BB_CLK2_A]	= &clk_rpmh_ln_bb_clk2_a4_ao.hw,

	[RPMH_LN_BB_CLK3]       = &clk_rpmh_ln_bb_clk3_a4.hw,

	[RPMH_LN_BB_CLK3_A]     = &clk_rpmh_ln_bb_clk3_a4_ao.hw,

	[RPMH_RF_CLK1]		= &clk_rpmh_rf_clk1_a.hw,

	[RPMH_RF_CLK1_A]	= &clk_rpmh_rf_clk1_a_ao.hw,

	[RPMH_RF_CLK5]		= &clk_rpmh_rf_clk5_a.hw,

	[RPMH_RF_CLK5_A]	= &clk_rpmh_rf_clk5_a_ao.hw,

	[RPMH_IPA_CLK]		= &clk_rpmh_ipa.hw,

};



static const struct clk_rpmh_desc clk_rpmh_sm4450 = {

	.clks = sm4450_rpmh_clocks,

	.num_clks = ARRAY_SIZE(sm4450_rpmh_clocks),

};



static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,

					 void *data)

{
@@ -810,6 +830,7 @@ static const struct of_device_id clk_rpmh_match_table[] = { 
	{ .compatible = "qcom,sdx55-rpmh-clk",  .data = &clk_rpmh_sdx55},

	{ .compatible = "qcom,sdx65-rpmh-clk",  .data = &clk_rpmh_sdx65},

	{ .compatible = "qcom,sdx75-rpmh-clk",  .data = &clk_rpmh_sdx75},

	{ .compatible = "qcom,sm4450-rpmh-clk", .data = &clk_rpmh_sm4450},

	{ .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350},

	{ .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},

	{ .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},