Commit 26579860 authored by Zhang Rui's avatar Zhang Rui Committed by Peter Zijlstra
Browse files

perf/x86/intel/cstate: Add Lunarlake support 



Compared with previous client platforms, PC8 is removed from Lunarlake.
It supports CC1/CC6/CC7 and PC2/PC3/PC6/PC10 residency counters.

Signed-off-by: default avatarZhang Rui <rui.zhang@intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Link: https://lore.kernel.org/r/20240628031758.43103-4-rui.zhang@intel.com
parent a3100075

arch/x86/events/intel/cstate.c

+19 −7
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ 
 *	MSR_CORE_C1_RES: CORE C1 Residency Counter

 *			 perf code: 0x00

 *			 Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL

 *					  MTL,SRF,GRR,ARL

 *					  MTL,SRF,GRR,ARL,LNL

 *			 Scope: Core (each processor core has a MSR)

 *	MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter

 *			       perf code: 0x01
@@ -53,31 +53,31 @@ 
 *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,

 *						SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,

 *						TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,

 *						GRR,ARL

 *						GRR,ARL,LNL

 *			       Scope: Core

 *	MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter

 *			       perf code: 0x03

 *			       Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,

 *						ICL,TGL,RKL,ADL,RPL,MTL,ARL

 *						ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL

 *			       Scope: Core

 *	MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.

 *			       perf code: 0x00

 *			       Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,

 *						KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,

 *						RPL,SPR,MTL,ARL

 *						RPL,SPR,MTL,ARL,LNL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.

 *			       perf code: 0x01

 *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,

 *						GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL,

 *						ADL,RPL,MTL,ARL

 *						ADL,RPL,MTL,ARL,LNL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C6_RESIDENCY:  Package C6 Residency Counter.

 *			       perf code: 0x02

 *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,

 *						SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,

 *						TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,

 *						ARL

 *						ARL,LNL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.

 *			       perf code: 0x03
@@ -96,7 +96,7 @@ 
 *	MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.

 *			       perf code: 0x06

 *			       Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,

 *						TNT,RKL,ADL,RPL,MTL,ARL

 *						TNT,RKL,ADL,RPL,MTL,ARL,LNL

 *			       Scope: Package (physical package)

 *	MSR_MODULE_C6_RES_MS:  Module C6 Residency Counter.

 *			       perf code: 0x00
@@ -640,6 +640,17 @@ static const struct cstate_model adl_cstates __initconst = { 
				  BIT(PERF_CSTATE_PKG_C10_RES),

};



static const struct cstate_model lnl_cstates __initconst = {

	.core_events		= BIT(PERF_CSTATE_CORE_C1_RES) |

				  BIT(PERF_CSTATE_CORE_C6_RES) |

				  BIT(PERF_CSTATE_CORE_C7_RES),



	.pkg_events		= BIT(PERF_CSTATE_PKG_C2_RES) |

				  BIT(PERF_CSTATE_PKG_C3_RES) |

				  BIT(PERF_CSTATE_PKG_C6_RES) |

				  BIT(PERF_CSTATE_PKG_C10_RES),

};



static const struct cstate_model slm_cstates __initconst = {

	.core_events		= BIT(PERF_CSTATE_CORE_C1_RES) |

				  BIT(PERF_CSTATE_CORE_C6_RES),
@@ -763,6 +774,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { 
	X86_MATCH_VFM(INTEL_ARROWLAKE,		&adl_cstates),

	X86_MATCH_VFM(INTEL_ARROWLAKE_H,	&adl_cstates),

	X86_MATCH_VFM(INTEL_ARROWLAKE_U,	&adl_cstates),

	X86_MATCH_VFM(INTEL_LUNARLAKE_M,	&lnl_cstates),

	{ },

};

MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);