Commit 2657a0c9 authored by Ilpo Järvinen's avatar Ilpo Järvinen Committed by Bjorn Helgaas
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m68k/PCI: Use pci_enable_resources() in pcibios_enable_device() 



m68k has a resource enable (check) loop in its pcibios_enable_device()
which for some reason differs from pci_enable_resources(). This could lead
to inconsistencies in behavior, especially now as pci_enable_resources()
and the bridge window resource flags behavior are going to be altered by
upcoming changes.

The check for !r->start && r->end is already covered by the more generic
checks done in pci_enable_resources().

The entire pcibios_enable_device() suspiciously looks copy-paste from some
other arch as also indicated by the preceding comment. However, it also
enables PCI_COMMAND_IO | PCI_COMMAND_MEMORY always for bridges. It is not
clear why that is being done as the commit e93a6bbe ("m68k: common PCI
support definitions and code") introducing this code states "Nothing
specific to any PCI implementation in any m68k class CPU hardware yet".

Replace the resource enable loop with a call to pci_enable_resources() and
adjust the Command Register afterwards as it's unclear if that is necessary
or not so keep it for now.

Signed-off-by: default avatarIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20250829131113.36754-2-ilpo.jarvinen@linux.intel.com
parent 31af09b3

arch/m68k/kernel/pcibios.c

+11 −28
Original line number Diff line number Diff line
@@ -44,42 +44,25 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res, 
 */

int pcibios_enable_device(struct pci_dev *dev, int mask)

{

	struct resource *r;

	u16 cmd, newcmd;

	int idx;

	int ret;



	pci_read_config_word(dev, PCI_COMMAND, &cmd);

	newcmd = cmd;



	for (idx = 0; idx < 6; idx++) {

		/* Only set up the requested stuff */

		if (!(mask & (1 << idx)))

			continue;



		r = dev->resource + idx;

		if (!r->start && r->end) {

			pr_err("PCI: Device %s not available because of resource collisions\n",

				pci_name(dev));

			return -EINVAL;

		}

		if (r->flags & IORESOURCE_IO)

			newcmd |= PCI_COMMAND_IO;

		if (r->flags & IORESOURCE_MEM)

			newcmd |= PCI_COMMAND_MEMORY;

	}

	ret = pci_enable_resources(dev, mask);

	if (ret < 0)

		return ret;



	/*

	 * Bridges (eg, cardbus bridges) need to be fully enabled

	 */

	if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)

	if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) {

		pci_read_config_word(dev, PCI_COMMAND, &cmd);

		newcmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;





		if (newcmd != cmd) {

		pr_info("PCI: enabling device %s (0x%04x -> 0x%04x)\n",

			pr_info("PCI: enabling bridge %s (0x%04x -> 0x%04x)\n",

				pci_name(dev), cmd, newcmd);

			pci_write_config_word(dev, PCI_COMMAND, newcmd);

		}

	}

	return 0;

}