Loading drivers/input/serio/i8042.c +28 −20 Original line number Diff line number Diff line Loading @@ -698,6 +698,26 @@ static void i8042_timer_func(unsigned long data) i8042_interrupt(0, NULL, NULL); } static int i8042_ctl_test(void) { unsigned char param; if (!i8042_reset) return 0; if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n"); return -1; } if (param != I8042_RET_CTL_TEST) { printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n", param, I8042_RET_CTL_TEST); return -1; } return 0; } /* * i8042_controller init initializes the i8042 controller, and, Loading @@ -719,21 +739,8 @@ static int i8042_controller_init(void) return -1; } if (i8042_reset) { unsigned char param; if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n"); if (i8042_ctl_test()) return -1; } if (param != I8042_RET_CTL_TEST) { printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n", param, I8042_RET_CTL_TEST); return -1; } } /* * Save the CTR for restoral on unload / reboot. Loading Loading @@ -806,9 +813,7 @@ static void i8042_controller_reset(void) * Reset the controller if requested. */ if (i8042_reset) if (i8042_command(¶m, I8042_CMD_CTL_TEST)) printk(KERN_ERR "i8042.c: i8042 controller reset timeout.\n"); i8042_ctl_test(); /* * Disable MUX mode if present. Loading Loading @@ -920,8 +925,11 @@ static int i8042_resume(struct device *dev, u32 level) if (level != RESUME_ENABLE) return 0; if (i8042_controller_init()) { printk(KERN_ERR "i8042: resume failed\n"); if (i8042_ctl_test()) return -1; if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { printk(KERN_ERR "i8042: Can't write CTR\n"); return -1; } Loading Loading
drivers/input/serio/i8042.c +28 −20 Original line number Diff line number Diff line Loading @@ -698,6 +698,26 @@ static void i8042_timer_func(unsigned long data) i8042_interrupt(0, NULL, NULL); } static int i8042_ctl_test(void) { unsigned char param; if (!i8042_reset) return 0; if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n"); return -1; } if (param != I8042_RET_CTL_TEST) { printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n", param, I8042_RET_CTL_TEST); return -1; } return 0; } /* * i8042_controller init initializes the i8042 controller, and, Loading @@ -719,21 +739,8 @@ static int i8042_controller_init(void) return -1; } if (i8042_reset) { unsigned char param; if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n"); if (i8042_ctl_test()) return -1; } if (param != I8042_RET_CTL_TEST) { printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n", param, I8042_RET_CTL_TEST); return -1; } } /* * Save the CTR for restoral on unload / reboot. Loading Loading @@ -806,9 +813,7 @@ static void i8042_controller_reset(void) * Reset the controller if requested. */ if (i8042_reset) if (i8042_command(¶m, I8042_CMD_CTL_TEST)) printk(KERN_ERR "i8042.c: i8042 controller reset timeout.\n"); i8042_ctl_test(); /* * Disable MUX mode if present. Loading Loading @@ -920,8 +925,11 @@ static int i8042_resume(struct device *dev, u32 level) if (level != RESUME_ENABLE) return 0; if (i8042_controller_init()) { printk(KERN_ERR "i8042: resume failed\n"); if (i8042_ctl_test()) return -1; if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { printk(KERN_ERR "i8042: Can't write CTR\n"); return -1; } Loading