Commit 2698fbb4 authored by Matthew Hagan's avatar Matthew Hagan Committed by Florian Fainelli
Browse files

ARM: dts: NSP: Add Ax stepping modifications 



While uncommon, some Ax NSP SoCs exist in the wild. This stepping
requires a modified secondary CPU boot-reg and removal of DMA coherency
properties. Without these modifications, the secondary CPU will be
inactive and many peripherals will exhibit undefined behaviour.

Signed-off-by: default avatarMatthew Hagan <mnhagan88@gmail.com>
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
parent f509d4a7

arch/arm/boot/dts/bcm-nsp-ax.dtsi

0 → 100644
+70 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

/*

 * Broadcom Northstar Plus Ax stepping-specific bindings.

 * Notable differences from B0+ are the secondary-boot-reg and

 * lack of DMA coherency.

 */



&cpu1 {

	secondary-boot-reg = <0xffff042c>;

};



&dma {

	/delete-property/ dma-coherent;

};



&sdio {

	/delete-property/ dma-coherent;

};



&amac0 {

	/delete-property/ dma-coherent;

};



&amac1 {

	/delete-property/ dma-coherent;

};



&amac2 {

	/delete-property/ dma-coherent;

};



&ehci0 {

	/delete-property/ dma-coherent;

};



&mailbox {

	/delete-property/ dma-coherent;

};



&xhci {

	/delete-property/ dma-coherent;

};



&ehci0 {

	/delete-property/ dma-coherent;

};



&ohci0 {

	/delete-property/ dma-coherent;

};



&i2c0 {

	/delete-property/ dma-coherent;

};



&sata {

	/delete-property/ dma-coherent;

};



&pcie0 {

	/delete-property/ dma-coherent;

};



&pcie1 {

	/delete-property/ dma-coherent;

};



&pcie2 {

	/delete-property/ dma-coherent;

};