Commit 26f2daa4 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: drop ih reroute function from psp v11 



For all the ASICs that integrate psp v11, vega20
doesn't support ih reroute. arcturus and later will
allow kernel driver to program ih_cfg_index/data
through mmio directly. navi1x and onwards will only
support grb_ih_set command in sriov configuration.

psp_v11_0_reroute_ih is not needed any more.

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 95c0c257

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

+0 −36
Original line number Diff line number Diff line
@@ -392,37 +392,6 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 
	return ret;

}



static void psp_v11_0_reroute_ih(struct psp_context *psp)

{

	struct amdgpu_device *adev = psp->adev;

	uint32_t tmp;



	/* Change IH ring for VMC */

	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);

	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);

	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);



	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);

	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);

	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);



	mdelay(20);

	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

		     0x80000000, 0x8000FFFF, false);



	/* Change IH ring for UMC */

	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);

	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);



	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);

	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);

	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);



	mdelay(20);

	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

		     0x80000000, 0x8000FFFF, false);

}



static int psp_v11_0_ring_init(struct psp_context *psp,

			      enum psp_ring_type ring_type)

{
@@ -430,11 +399,6 @@ static int psp_v11_0_ring_init(struct psp_context *psp, 
	struct psp_ring *ring;

	struct amdgpu_device *adev = psp->adev;



	if ((!amdgpu_sriov_vf(adev)) &&

	    !(adev->asic_type >= CHIP_SIENNA_CICHLID &&

	    adev->asic_type <= CHIP_DIMGREY_CAVEFISH))

		psp_v11_0_reroute_ih(psp);



	ring = &psp->km_ring;



	ring->ring_type = ring_type;