Commit 2739bd12 authored by Dmytro's avatar Dmytro Committed by Alex Deucher
Browse files

drm/amd/display: Allow reuse of of DCN4x code 



Remove the static qualifier to make it available for code sharing
with other components.

Reviewed-by: default avatarCharlene Liu <charlene.liu@amd.com>
Signed-off-by: default avatarDmytro <dmytro.laktyushkin@amd.com>
Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Signed-off-by: default avatarAlex Hung <alex.hung@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 503d6748

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

+12 −12
Original line number Diff line number Diff line
@@ -116,7 +116,7 @@ static void dccg401_wait_for_dentist_change_done( 
	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);

}



static void dccg401_get_pixel_rate_div(

void dccg401_get_pixel_rate_div(

		struct dccg *dccg,

		uint32_t otg_inst,

		uint32_t *tmds_div,
@@ -154,7 +154,7 @@ static void dccg401_get_pixel_rate_div( 
	*tmds_div = val_tmds_div == 0 ? PIXEL_RATE_DIV_BY_2 : PIXEL_RATE_DIV_BY_4;

}



static void dccg401_set_pixel_rate_div(

void dccg401_set_pixel_rate_div(

		struct dccg *dccg,

		uint32_t otg_inst,

		enum pixel_rate_div tmds_div,
@@ -209,7 +209,7 @@ static void dccg401_set_pixel_rate_div( 
}





static void dccg401_set_dtbclk_p_src(

void dccg401_set_dtbclk_p_src(

		struct dccg *dccg,

		enum streamclk_source src,

		uint32_t otg_inst)
@@ -348,7 +348,7 @@ void dccg401_set_physymclk( 
	}

}



static void dccg401_get_dccg_ref_freq(struct dccg *dccg,

void dccg401_get_dccg_ref_freq(struct dccg *dccg,

		unsigned int xtalin_freq_inKhz,

		unsigned int *dccg_ref_freq_inKhz)

{
@@ -378,7 +378,7 @@ static void dccg401_otg_drop_pixel(struct dccg *dccg, 
			OTG_DROP_PIXEL[otg_inst], 1);

}



static void dccg401_enable_symclk32_le(

void dccg401_enable_symclk32_le(

		struct dccg *dccg,

		int hpo_le_inst,

		enum phyd32clk_clock_source phyd32clk)
@@ -429,7 +429,7 @@ static void dccg401_enable_symclk32_le( 
	}

}



static void dccg401_disable_symclk32_le(

void dccg401_disable_symclk32_le(

		struct dccg *dccg,

		int hpo_le_inst)

{
@@ -574,7 +574,7 @@ static void dccg401_disable_dpstreamclk(struct dccg *dccg, int dp_hpo_inst) 
	}

}



static void dccg401_set_dpstreamclk(

void dccg401_set_dpstreamclk(

		struct dccg *dccg,

		enum streamclk_source src,

		int otg_inst,
@@ -587,7 +587,7 @@ static void dccg401_set_dpstreamclk( 
		dccg401_enable_dpstreamclk(dccg, otg_inst, dp_hpo_inst);

}



static void dccg401_set_dp_dto(

void dccg401_set_dp_dto(

		struct dccg *dccg,

		const struct dp_dto_params *params)

{
@@ -727,7 +727,7 @@ void dccg401_init(struct dccg *dccg) 
	}

}



static void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst)

void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
@@ -763,7 +763,7 @@ static void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst) 
	}

}



static void dccg401_set_ref_dscclk(struct dccg *dccg,

void dccg401_set_ref_dscclk(struct dccg *dccg,

				uint32_t dsc_inst)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
@@ -798,7 +798,7 @@ static void dccg401_set_ref_dscclk(struct dccg *dccg, 
	}

}



static void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
@@ -834,7 +834,7 @@ static void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst 
	}

}



static void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

+39 −1
Original line number Diff line number Diff line
@@ -193,10 +193,48 @@ 
void dccg401_init(struct dccg *dccg);



void dccg401_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);



void dccg401_get_dccg_ref_freq(struct dccg *dccg,

		unsigned int xtalin_freq_inKhz,

		unsigned int *dccg_ref_freq_inKhz);

void dccg401_set_dpstreamclk(

		struct dccg *dccg,

		enum streamclk_source src,

		int otg_inst,

		int dp_hpo_inst);

void dccg401_enable_symclk32_le(

		struct dccg *dccg,

		int hpo_le_inst,

		enum phyd32clk_clock_source phyd32clk);

void dccg401_disable_symclk32_le(

		struct dccg *dccg,

		int hpo_le_inst);

void dccg401_set_ref_dscclk(struct dccg *dccg,

				uint32_t dsc_inst);

void dccg401_set_src_sel(

	struct dccg *dccg,

	const struct dtbclk_dto_params *params);

void dccg401_set_pixel_rate_div(

		struct dccg *dccg,

		uint32_t otg_inst,

		enum pixel_rate_div tmds_div,

		enum pixel_rate_div unused);

void dccg401_get_pixel_rate_div(

		struct dccg *dccg,

		uint32_t otg_inst,

		uint32_t *tmds_div,

		uint32_t *dp_dto_int);

void dccg401_set_dp_dto(

		struct dccg *dccg,

		const struct dp_dto_params *params);

void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);

void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);



void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst);

void dccg401_set_dtbclk_p_src(

		struct dccg *dccg,

		enum streamclk_source src,

		uint32_t otg_inst);





struct dccg *dccg401_create(

	struct dc_context *ctx,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

+1 −1
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@ 
	enc1->base.ctx





static void enc3_update_hdmi_info_packet(

void enc3_update_hdmi_info_packet(

	struct dcn10_stream_encoder *enc1,

	uint32_t packet_index,

	const struct dc_info_packet *info_packet)

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

+5 −1
Original line number Diff line number Diff line
@@ -323,5 +323,9 @@ void enc3_dp_set_dsc_pps_info_packet( 
	bool enable,

	uint8_t *dsc_packed_pps,

	bool immediate_update);

void enc3_update_hdmi_info_packet(

	struct dcn10_stream_encoder *enc1,

	uint32_t packet_index,

	const struct dc_info_packet *info_packet);



#endif /* __DC_DIO_STREAM_ENCODER_DCN30_H__ */

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

+6 −6
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ static void enc401_dp_set_odm_combine( 
}



/* setup stream encoder in dvi mode */

static void enc401_stream_encoder_dvi_set_stream_attribute(

void enc401_stream_encoder_dvi_set_stream_attribute(

	struct stream_encoder *enc,

	struct dc_crtc_timing *crtc_timing,

	bool is_dual_link)
@@ -229,7 +229,7 @@ static void enc401_stream_encoder_hdmi_set_stream_attribute( 
	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);

}



static void enc401_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container)

void enc401_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container)

{

	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
@@ -260,7 +260,7 @@ static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing) 
	return two_pix;

}



static void enc401_stream_encoder_dp_unblank(

void enc401_stream_encoder_dp_unblank(

		struct dc_link *link,

		struct stream_encoder *enc,

		const struct encoder_unblank_param *param)
@@ -376,7 +376,7 @@ static void enc401_stream_encoder_dp_unblank( 
/* this function read dsc related register fields to be logged later in dcn10_log_hw_state

 * into a dcn_dsc_state struct.

 */

static void enc401_read_state(struct stream_encoder *enc, struct enc_state *s)

void enc401_read_state(struct stream_encoder *enc, struct enc_state *s)

{

	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
@@ -394,7 +394,7 @@ static void enc401_read_state(struct stream_encoder *enc, struct enc_state *s) 
	}

}



static void enc401_stream_encoder_enable(

void enc401_stream_encoder_enable(

	struct stream_encoder *enc,

	enum signal_type signal,

	bool enable)
@@ -704,7 +704,7 @@ void enc401_stream_encoder_dp_set_stream_attribute( 
		DP_SST_SDP_SPLITTING, enable_sdp_splitting);

}



static void enc401_stream_encoder_map_to_link(

void enc401_stream_encoder_map_to_link(

		struct stream_encoder *enc,

		uint32_t stream_enc_inst,

		uint32_t link_enc_inst)