Commit 27442c5f authored by Uma Shankar's avatar Uma Shankar
Browse files

drm/i915: Extract DSPCLK_GATE_D from i915_reg to display 



Move DSPCLK_GATE_D register definition to display header.
This allows intel_gmbus.c not to include i915_reg.h.

v3: Update commit header and message (Jani)

v2: Drop common header in include and use display_regs.h (Jani)

Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarUma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-5-uma.shankar@intel.com
parent b425c278

drivers/gpu/drm/i915/display/intel_display_regs.h

+50 −0
Original line number Diff line number Diff line
@@ -160,6 +160,47 @@ 


#define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000



#define DSPCLK_GATE_D			_MMIO(0x6200)

#define VLV_DSPCLK_GATE_D		_MMIO(VLV_DISPLAY_BASE + 0x6200)

# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */

# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */

# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */

# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */

# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */

# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */

# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */

# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE	(1 << 24) /* pnv */

# define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */

# define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */

# define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */

# define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */

# define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */

# define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */

# define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */

# define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */

# define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */

# define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */

# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */

# define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */

# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)

# define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)

# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)

# define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)

# define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */

# define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */

# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */

# define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)

# define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)

/*

 * This bit must be set on the 830 to prevent hangs when turning off the

 * overlay scaler.

 */

# define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)

# define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)

# define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)

# define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */

# define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */



/* Additional CHV pll/phy registers */

#define DPIO_PHY_STATUS			_MMIO(VLV_DISPLAY_BASE + 0x6240)

#define   DPLL_PORTD_READY_MASK		(0xf)
@@ -2931,6 +2972,15 @@ enum skl_power_gate { 
#define  LPT_PWM_GRANULARITY		(1 << 5)

#define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)



#define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)

#define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)

#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)

#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)

#define  PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)

#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)

#define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)

#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)



/* Gen4+ Timestamp and Pipe Frame time stamp registers */

#define GEN4_TIMESTAMP		_MMIO(0x2358)

#define ILK_TIMESTAMP_HI	_MMIO(0x70070)

drivers/gpu/drm/i915/display/intel_gmbus.c

+0 −1
Original line number Diff line number Diff line
@@ -35,7 +35,6 @@ 
#include <drm/drm_print.h>

#include <drm/display/drm_hdcp_helper.h>



#include "i915_reg.h"

#include "intel_de.h"

#include "intel_display_regs.h"

#include "intel_display_types.h"

drivers/gpu/drm/i915/i915_reg.h

+0 −50
Original line number Diff line number Diff line
@@ -613,47 +613,6 @@ 
#define  DSTATE_GFX_CLOCK_GATING		(1 << 1)

#define  DSTATE_DOT_CLOCK_GATING		(1 << 0)



#define DSPCLK_GATE_D			_MMIO(0x6200)

#define VLV_DSPCLK_GATE_D		_MMIO(VLV_DISPLAY_BASE + 0x6200)

# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */

# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */

# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */

# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */

# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */

# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */

# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */

# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE	(1 << 24) /* pnv */

# define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */

# define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */

# define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */

# define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */

# define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */

# define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */

# define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */

# define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */

# define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */

# define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */

# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */

# define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */

# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)

# define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)

# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)

# define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)

# define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */

# define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */

# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */

# define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)

# define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)

/*

 * This bit must be set on the 830 to prevent hangs when turning off the

 * overlay scaler.

 */

# define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)

# define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)

# define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)

# define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */

# define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */



#define RENCLK_GATE_D1		_MMIO(0x6204)

# define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */

# define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
@@ -990,15 +949,6 @@ 
#define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)

#define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)



#define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)

#define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)

#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)

#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)

#define  PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)

#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)

#define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)

#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)



#define  VLV_PMWGICZ				_MMIO(0x1300a4)



#define  HSW_EDRAM_CAP				_MMIO(0x120010)