Commit 27650969 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

PCI: imx6: Move imx6_pcie_enable_ref_clk() earlier 

Move imx6_pcie_enable_ref_clk() earlier so it's not in the middle between
imx6_pcie_assert_core_reset() and imx6_pcie_deassert_core_reset().  No
functional change intended.

Link: https://lore.kernel.org/r/1657783869-19194-4-git-send-email-hongxing.zhu@nxp.com


Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarLucas Stach <l.stach@pengutronix.de>
Acked-by: default avatarRichard Zhu <hongxing.zhu@nxp.com>
parent 6b1e989e

drivers/pci/controller/dwc/pci-imx6.c

+48 −48
Original line number Diff line number Diff line
@@ -520,54 +520,6 @@ static int imx6_pcie_attach_pd(struct device *dev) 
	return 0;

}



static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)

{

	struct device *dev = imx6_pcie->pci->dev;



	switch (imx6_pcie->drvdata->variant) {

	case IMX7D:

	case IMX8MQ:

		reset_control_assert(imx6_pcie->pciephy_reset);

		fallthrough;

	case IMX8MM:

		reset_control_assert(imx6_pcie->apps_reset);

		break;

	case IMX6SX:

		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,

				   IMX6SX_GPR12_PCIE_TEST_POWERDOWN,

				   IMX6SX_GPR12_PCIE_TEST_POWERDOWN);

		/* Force PCIe PHY reset */

		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,

				   IMX6SX_GPR5_PCIE_BTNRST_RESET,

				   IMX6SX_GPR5_PCIE_BTNRST_RESET);

		break;

	case IMX6QP:

		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,

				   IMX6Q_GPR1_PCIE_SW_RST,

				   IMX6Q_GPR1_PCIE_SW_RST);

		break;

	case IMX6Q:

		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,

				   IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);

		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,

				   IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);

		break;

	}



	if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {

		int ret = regulator_disable(imx6_pcie->vpcie);



		if (ret)

			dev_err(dev, "failed to disable vpcie regulator: %d\n",

				ret);

	}



	/* Some boards don't have PCIe reset GPIO. */

	if (gpio_is_valid(imx6_pcie->reset_gpio))

		gpio_set_value_cansleep(imx6_pcie->reset_gpio,

					imx6_pcie->gpio_active_high);

}



static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)

{

	struct dw_pcie *pci = imx6_pcie->pci;
@@ -628,6 +580,54 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) 
	return ret;

}



static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)

{

	struct device *dev = imx6_pcie->pci->dev;



	switch (imx6_pcie->drvdata->variant) {

	case IMX7D:

	case IMX8MQ:

		reset_control_assert(imx6_pcie->pciephy_reset);

		fallthrough;

	case IMX8MM:

		reset_control_assert(imx6_pcie->apps_reset);

		break;

	case IMX6SX:

		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,

				   IMX6SX_GPR12_PCIE_TEST_POWERDOWN,

				   IMX6SX_GPR12_PCIE_TEST_POWERDOWN);

		/* Force PCIe PHY reset */

		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,

				   IMX6SX_GPR5_PCIE_BTNRST_RESET,

				   IMX6SX_GPR5_PCIE_BTNRST_RESET);

		break;

	case IMX6QP:

		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,

				   IMX6Q_GPR1_PCIE_SW_RST,

				   IMX6Q_GPR1_PCIE_SW_RST);

		break;

	case IMX6Q:

		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,

				   IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);

		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,

				   IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);

		break;

	}



	if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {

		int ret = regulator_disable(imx6_pcie->vpcie);



		if (ret)

			dev_err(dev, "failed to disable vpcie regulator: %d\n",

				ret);

	}



	/* Some boards don't have PCIe reset GPIO. */

	if (gpio_is_valid(imx6_pcie->reset_gpio))

		gpio_set_value_cansleep(imx6_pcie->reset_gpio,

					imx6_pcie->gpio_active_high);

}



static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)

{

	struct dw_pcie *pci = imx6_pcie->pci;