Commit 27727cb6 authored by Johan Hovold's avatar Johan Hovold Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: x1e80100: fix PCIe4 and PCIe6a PHY clocks 



Add the missing clkref enable and pipediv2 clocks to the PCIe4 and
PCIe6a PHYs.

Fixes: 5eb83fc1 ("arm64: dts: qcom: x1e80100: Add PCIe nodes")
Cc: stable@vger.kernel.org	# 6.9
Cc: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: default avatarJohan Hovold <johan+linaro@kernel.org>
Reviewed-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konradybcio@kernel.org>
Link: https://lore.kernel.org/r/20240916082307.29393-3-johan+linaro@kernel.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 9852d85e

arch/arm64/boot/dts/qcom/x1e80100.dtsi

+10 −6
Original line number Diff line number Diff line
@@ -3002,14 +3002,16 @@ pcie6a_phy: phy@1bfc000 { 


			clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>,

				 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,

				 <&rpmhcc RPMH_CXO_CLK>,

				 <&tcsr TCSR_PCIE_4L_CLKREF_EN>,

				 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>,

				 <&gcc GCC_PCIE_6A_PIPE_CLK>;

				 <&gcc GCC_PCIE_6A_PIPE_CLK>,

				 <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>;

			clock-names = "aux",

				      "cfg_ahb",

				      "ref",

				      "rchng",

				      "pipe";

				      "pipe",

				      "pipediv2";



			resets = <&gcc GCC_PCIE_6A_PHY_BCR>,

				 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>;
@@ -3254,14 +3256,16 @@ pcie4_phy: phy@1c0e000 { 


			clocks = <&gcc GCC_PCIE_4_AUX_CLK>,

				 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,

				 <&rpmhcc RPMH_CXO_CLK>,

				 <&tcsr TCSR_PCIE_2L_4_CLKREF_EN>,

				 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>,

				 <&gcc GCC_PCIE_4_PIPE_CLK>;

				 <&gcc GCC_PCIE_4_PIPE_CLK>,

				 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;

			clock-names = "aux",

				      "cfg_ahb",

				      "ref",

				      "rchng",

				      "pipe";

				      "pipe",

				      "pipediv2";



			resets = <&gcc GCC_PCIE_4_PHY_BCR>;

			reset-names = "phy";