Commit 279d519f authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: add dispclk ramping to dcn35. 



[why]
this is a required logic based on HW programming guide.
tested/ported on dcn401.

Reviewed-by: default avatarYihan Zhu <yihan.zhu@amd.com>
Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f9491b67

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

+12 −0
Original line number Diff line number Diff line
@@ -1114,6 +1114,16 @@ static void dccg35_trigger_dio_fifo_resync(struct dccg *dccg) 
	if (dispclk_rdivider_value != 0)

		REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value);

}

static void dccg35_wait_for_dentist_change_done(

	struct dccg *dccg)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);



	uint32_t dentist_dispclk_value = REG_READ(DENTIST_DISPCLK_CNTL);



	REG_WRITE(DENTIST_DISPCLK_CNTL, dentist_dispclk_value);

	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);

}



static void dcn35_set_dppclk_enable(struct dccg *dccg,

				 uint32_t dpp_inst, uint32_t enable)
@@ -1300,6 +1310,8 @@ static void dccg35_set_pixel_rate_div( 
		BREAK_TO_DEBUGGER();

		return;

	}

	if (otg_inst < 4)

		dccg35_wait_for_dentist_change_done(dccg);

}



static void dccg35_set_dtbclk_p_src(