Commit 27c41353 authored by Sean Christopherson's avatar Sean Christopherson
Browse files

KVM: selftests: Add support for MSR_IA32_{S,U}_CET to MSRs test 



Extend the MSRs test to support {S,U}_CET, which are a bit of a pain to
handled due to the MSRs existing if IBT *or* SHSTK is supported.  To deal
with Intel's wonderful decision to bundle IBT and SHSTK under CET, track
the second feature, but skip only RDMSR #GP tests to avoid false failures
when running on a CPU with only one of IBT or SHSTK (the WRMSR #GP tests
are still valid since the enable bits are per-feature).

Reviewed-by: default avatarChao Gao <chao.gao@intel.com>
Link: https://lore.kernel.org/r/20250919223258.1604852-47-seanjc@google.com


Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
parent 9c38ddb3

tools/testing/selftests/kvm/x86/msrs_test.c

+19 −2
Original line number Diff line number Diff line
@@ -132,13 +132,26 @@ static void guest_test_unsupported_msr(const struct kvm_msr *msr) 
	if (ignore_unsupported_msrs)

		goto skip_wrmsr_gp;



	if (this_cpu_has(msr->feature2))

	/*

	 * {S,U}_CET exist if IBT or SHSTK is supported, but with bits that are

	 * writable only if their associated feature is supported.  Skip the

	 * RDMSR #GP test if the secondary feature is supported, but perform

	 * the WRMSR #GP test as the to-be-written value is tied to the primary

	 * feature.  For all other MSRs, simply do nothing.

	 */

	if (this_cpu_has(msr->feature2)) {

		if  (msr->index != MSR_IA32_U_CET &&

		     msr->index != MSR_IA32_S_CET)

			goto skip_wrmsr_gp;



		goto skip_rdmsr_gp;

	}



	vec = rdmsr_safe(msr->index, &val);

	__GUEST_ASSERT(vec == GP_VECTOR, "Wanted #GP on RDMSR(0x%x), got %s",

		       msr->index, ex_str(vec));



skip_rdmsr_gp:

	vec = wrmsr_safe(msr->index, msr->write_val);

	__GUEST_ASSERT(vec == GP_VECTOR, "Wanted #GP on WRMSR(0x%x, 0x%lx), got %s",

		       msr->index, msr->write_val, ex_str(vec));
@@ -276,6 +289,10 @@ static void test_msrs(void) 
		MSR_TEST_CANONICAL(MSR_CSTAR, LM),

		MSR_TEST(MSR_SYSCALL_MASK, 0xffffffff, 0, LM),



		MSR_TEST2(MSR_IA32_S_CET, CET_SHSTK_EN, CET_RESERVED, SHSTK, IBT),

		MSR_TEST2(MSR_IA32_S_CET, CET_ENDBR_EN, CET_RESERVED, IBT, SHSTK),

		MSR_TEST2(MSR_IA32_U_CET, CET_SHSTK_EN, CET_RESERVED, SHSTK, IBT),

		MSR_TEST2(MSR_IA32_U_CET, CET_ENDBR_EN, CET_RESERVED, IBT, SHSTK),

		MSR_TEST_CANONICAL(MSR_IA32_PL0_SSP, SHSTK),

		MSR_TEST(MSR_IA32_PL0_SSP, canonical_val, canonical_val | 1, SHSTK),

		MSR_TEST_CANONICAL(MSR_IA32_PL1_SSP, SHSTK),