Commit 27f3d3f6 authored by André Draszik's avatar André Draszik Committed by Vinod Koul
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phy: exynos5-usbdrd: convert udelay() to fsleep() 



The timers-howto recommends using usleep_range() and friends anytime
waiting for >= ~10us is required. Doing so can help the timer subsystem
a lot to coalesce wakeups.

Additionally, fsleep() exists as a convenient wrapper so we do not have
to think about which exact sleeping function is required in which case.

Convert all udelay() calls in this driver to use fsleep() to follow the
recommendataion.

Signed-off-by: default avatarAndré Draszik <andre.draszik@linaro.org>
Reviewed-by: default avatarPeter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240507-samsung-usb-phy-fixes-v1-2-4ccba5afa7cc@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 2a0dc34b

drivers/phy/samsung/phy-exynos5-usbdrd.c

+4 −4
Original line number Diff line number Diff line
@@ -448,7 +448,7 @@ static int exynos5_usbdrd_phy_init(struct phy *phy) 


	writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);



	udelay(10);

	fsleep(10);



	reg &= ~PHYCLKRST_PORTRESET;

	writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
@@ -779,11 +779,11 @@ static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) 
	writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST);



	/* Finish PHY reset (POR=low) */

	udelay(10); /* required before doing POR=low */

	fsleep(10); /* required before doing POR=low */

	reg = readl(regs_base + EXYNOS850_DRD_CLKRST);

	reg &= ~(CLKRST_PHY_SW_RST | CLKRST_PORT_RST);

	writel(reg, regs_base + EXYNOS850_DRD_CLKRST);

	udelay(75); /* required after POR=low for guaranteed PHY clock */

	fsleep(75); /* required after POR=low for guaranteed PHY clock */



	/* Disable single ended signal out */

	reg = readl(regs_base + EXYNOS850_DRD_HSP);
@@ -836,7 +836,7 @@ static int exynos850_usbdrd_phy_exit(struct phy *phy) 
	reg = readl(regs_base + EXYNOS850_DRD_CLKRST);

	reg |= CLKRST_LINK_SW_RST;

	writel(reg, regs_base + EXYNOS850_DRD_CLKRST);

	udelay(10); /* required before doing POR=low */

	fsleep(10); /* required before doing POR=low */

	reg &= ~CLKRST_LINK_SW_RST;

	writel(reg, regs_base + EXYNOS850_DRD_CLKRST);