Commit 280b7cdd authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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dt-bindings: clock: renesas,r9a09g057-cpg: Add USB3.0 core clocks

parent 3a866087
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+4 −0
Original line number Diff line number Diff line
@@ -22,5 +22,9 @@
#define R9A09G057_GBETH_0_CLK_PTP_REF_I		11
#define R9A09G057_GBETH_1_CLK_PTP_REF_I		12
#define R9A09G057_SPI_CLK_SPI			13
#define R9A09G057_USB3_0_REF_ALT_CLK_P		14
#define R9A09G057_USB3_0_CLKCORE		15
#define R9A09G057_USB3_1_REF_ALT_CLK_P		16
#define R9A09G057_USB3_1_CLKCORE		17

#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */