Commit 28307372 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-6.19-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 

Pull RISC-V fixes from Paul Walmsley:

 - Correct the RISC-V compat.h COMPAT_UTS_MACHINE architecture name

 - Avoid printing a false warning message on kernels with the SiFive and
   MIPS errata compiled in

 - Address a few warnings generated by sparse in the signal handling
   code

 - Fix a comment typo

* tag 'riscv-for-linus-6.19-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: compat: fix COMPAT_UTS_MACHINE definition
  errata/sifive: remove unreliable warn_miss_errata
  riscv: fix minor typo in syscall.h comment
  riscv: signal: fix some warnings reported by sparse
parents 367b81ef 0ea05c4f

arch/riscv/errata/sifive/errata.c

+0 −18
Original line number Diff line number Diff line
@@ -75,26 +75,12 @@ static u32 __init_or_module sifive_errata_probe(unsigned long archid, 
	return cpu_req_errata;

}



static void __init_or_module warn_miss_errata(u32 miss_errata)

{

	int i;



	pr_warn("----------------------------------------------------------------\n");

	pr_warn("WARNING: Missing the following errata may cause potential issues\n");

	for (i = 0; i < ERRATA_SIFIVE_NUMBER; i++)

		if (miss_errata & 0x1 << i)

			pr_warn("\tSiFive Errata[%d]:%s\n", i, errata_list[i].name);

	pr_warn("Please enable the corresponding Kconfig to apply them\n");

	pr_warn("----------------------------------------------------------------\n");

}



void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,

			      unsigned long archid, unsigned long impid,

			      unsigned int stage)

{

	struct alt_entry *alt;

	u32 cpu_req_errata;

	u32 cpu_apply_errata = 0;

	u32 tmp;



	BUILD_BUG_ON(ERRATA_SIFIVE_NUMBER >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE);
@@ -118,10 +104,6 @@ void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, 
			patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt),

					  alt->alt_len);

			mutex_unlock(&text_mutex);

			cpu_apply_errata |= tmp;

		}

	}

	if (stage != RISCV_ALTERNATIVES_MODULE &&

	    cpu_apply_errata != cpu_req_errata)

		warn_miss_errata(cpu_req_errata - cpu_apply_errata);

}

arch/riscv/include/asm/compat.h

+1 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
#ifndef __ASM_COMPAT_H

#define __ASM_COMPAT_H



#define COMPAT_UTS_MACHINE	"riscv\0\0"

#define COMPAT_UTS_MACHINE	"riscv32\0\0"



/*

 * Architecture specific compatibility types

arch/riscv/include/asm/syscall.h

+1 −1
Original line number Diff line number Diff line
@@ -20,7 +20,7 @@ extern void * const sys_call_table[]; 
extern void * const compat_sys_call_table[];



/*

 * Only the low 32 bits of orig_r0 are meaningful, so we return int.

 * Only the low 32 bits of orig_a0 are meaningful, so we return int.

 * This importantly ignores the high bits on 64-bit, so comparisons

 * sign-extend the low 32 bits.

 */

arch/riscv/kernel/signal.c

+3 −3
Original line number Diff line number Diff line
@@ -145,14 +145,14 @@ struct arch_ext_priv { 
	long (*save)(struct pt_regs *regs, void __user *sc_vec);

};



struct arch_ext_priv arch_ext_list[] = {

static struct arch_ext_priv arch_ext_list[] = {

	{

		.magic = RISCV_V_MAGIC,

		.save = &save_v_state,

	},

};



const size_t nr_arch_exts = ARRAY_SIZE(arch_ext_list);

static const size_t nr_arch_exts = ARRAY_SIZE(arch_ext_list);



static long restore_sigcontext(struct pt_regs *regs,

	struct sigcontext __user *sc)
@@ -297,7 +297,7 @@ static long setup_sigcontext(struct rt_sigframe __user *frame, 
		} else {

			err |= __put_user(arch_ext->magic, &sc_ext_ptr->magic);

			err |= __put_user(ext_size, &sc_ext_ptr->size);

			sc_ext_ptr = (void *)sc_ext_ptr + ext_size;

			sc_ext_ptr = (void __user *)sc_ext_ptr + ext_size;

		}

	}

	/* Write zero to fp-reserved space and check it on restore_sigcontext */