Loading include/asm-x86/bitops.h +13 −24 Original line number Diff line number Diff line Loading @@ -48,9 +48,7 @@ */ static inline void set_bit(int nr, volatile void *addr) { asm volatile(LOCK_PREFIX "bts %1,%0" : ADDR : "Ir" (nr) : "memory"); asm volatile(LOCK_PREFIX "bts %1,%0" : ADDR : "Ir" (nr) : "memory"); } /** Loading Loading @@ -82,8 +80,7 @@ static inline void __set_bit(int nr, volatile void *addr) */ static inline void clear_bit(int nr, volatile void *addr) { asm volatile(LOCK_PREFIX "btr %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR); asm volatile(LOCK_PREFIX "btr %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR); } /* Loading Loading @@ -151,8 +148,7 @@ static inline void __change_bit(int nr, volatile void *addr) */ static inline void change_bit(int nr, volatile void *addr) { asm volatile(LOCK_PREFIX "btc %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR); asm volatile(LOCK_PREFIX "btc %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR); } /** Loading @@ -168,9 +164,7 @@ static inline int test_and_set_bit(int nr, volatile void *addr) int oldbit; asm volatile(LOCK_PREFIX "bts %2,%1\n\t" "sbb %0,%0" : "=r" (oldbit), ADDR : "Ir" (nr) : "memory"); "sbb %0,%0" : "=r" (oldbit), ADDR : "Ir" (nr) : "memory"); return oldbit; } Loading Loading @@ -202,8 +196,7 @@ static inline int __test_and_set_bit(int nr, volatile void *addr) asm volatile("bts %2,%3\n\t" "sbb %0,%0" : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR); : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR); return oldbit; } Loading @@ -221,8 +214,7 @@ static inline int test_and_clear_bit(int nr, volatile void *addr) asm volatile(LOCK_PREFIX "btr %2,%1\n\t" "sbb %0,%0" : "=r" (oldbit), ADDR : "Ir" (nr) : "memory"); : "=r" (oldbit), ADDR : "Ir" (nr) : "memory"); return oldbit; } Loading @@ -242,8 +234,7 @@ static inline int __test_and_clear_bit(int nr, volatile void *addr) asm volatile("btr %2,%3\n\t" "sbb %0,%0" : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR); : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR); return oldbit; } Loading @@ -254,8 +245,7 @@ static inline int __test_and_change_bit(int nr, volatile void *addr) asm volatile("btc %2,%3\n\t" "sbb %0,%0" : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR); : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR); return oldbit; } Loading @@ -274,8 +264,7 @@ static inline int test_and_change_bit(int nr, volatile void *addr) asm volatile(LOCK_PREFIX "btc %2,%1\n\t" "sbb %0,%0" : "=r" (oldbit), ADDR : "Ir" (nr) : "memory"); : "=r" (oldbit), ADDR : "Ir" (nr) : "memory"); return oldbit; } Loading Loading
include/asm-x86/bitops.h +13 −24 Original line number Diff line number Diff line Loading @@ -48,9 +48,7 @@ */ static inline void set_bit(int nr, volatile void *addr) { asm volatile(LOCK_PREFIX "bts %1,%0" : ADDR : "Ir" (nr) : "memory"); asm volatile(LOCK_PREFIX "bts %1,%0" : ADDR : "Ir" (nr) : "memory"); } /** Loading Loading @@ -82,8 +80,7 @@ static inline void __set_bit(int nr, volatile void *addr) */ static inline void clear_bit(int nr, volatile void *addr) { asm volatile(LOCK_PREFIX "btr %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR); asm volatile(LOCK_PREFIX "btr %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR); } /* Loading Loading @@ -151,8 +148,7 @@ static inline void __change_bit(int nr, volatile void *addr) */ static inline void change_bit(int nr, volatile void *addr) { asm volatile(LOCK_PREFIX "btc %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR); asm volatile(LOCK_PREFIX "btc %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR); } /** Loading @@ -168,9 +164,7 @@ static inline int test_and_set_bit(int nr, volatile void *addr) int oldbit; asm volatile(LOCK_PREFIX "bts %2,%1\n\t" "sbb %0,%0" : "=r" (oldbit), ADDR : "Ir" (nr) : "memory"); "sbb %0,%0" : "=r" (oldbit), ADDR : "Ir" (nr) : "memory"); return oldbit; } Loading Loading @@ -202,8 +196,7 @@ static inline int __test_and_set_bit(int nr, volatile void *addr) asm volatile("bts %2,%3\n\t" "sbb %0,%0" : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR); : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR); return oldbit; } Loading @@ -221,8 +214,7 @@ static inline int test_and_clear_bit(int nr, volatile void *addr) asm volatile(LOCK_PREFIX "btr %2,%1\n\t" "sbb %0,%0" : "=r" (oldbit), ADDR : "Ir" (nr) : "memory"); : "=r" (oldbit), ADDR : "Ir" (nr) : "memory"); return oldbit; } Loading @@ -242,8 +234,7 @@ static inline int __test_and_clear_bit(int nr, volatile void *addr) asm volatile("btr %2,%3\n\t" "sbb %0,%0" : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR); : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR); return oldbit; } Loading @@ -254,8 +245,7 @@ static inline int __test_and_change_bit(int nr, volatile void *addr) asm volatile("btc %2,%3\n\t" "sbb %0,%0" : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR); : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR); return oldbit; } Loading @@ -274,8 +264,7 @@ static inline int test_and_change_bit(int nr, volatile void *addr) asm volatile(LOCK_PREFIX "btc %2,%1\n\t" "sbb %0,%0" : "=r" (oldbit), ADDR : "Ir" (nr) : "memory"); : "=r" (oldbit), ADDR : "Ir" (nr) : "memory"); return oldbit; } Loading