Commit 28899037 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2026-03-30' of... 

Merge tag 'drm-intel-next-2026-03-30' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-next

drm/i915 feature pull #2 for v7.1:

Refactoring and cleanups:
- Refactor LT PHY PLL handling to use the DPLL framework (Mika)
- Implement display register polling and waits in display code (Ville)
- Move PCH clock gating in display PCH file (Luca)
- Add shared stepping info header for i915 and display (Jani)
- Clean up GVT I2C command decoding (Jonathan)
- NV12 plane unlinking cleanups (Ville)
- Clean up NV12 DDB/watermark handling for pre-ICL platforms (Ville)

Fixes:
- An assortment of DSI fixes (Ville)
- Handle PORT_NONE in assert_port_valid() (Jonathan)
- Fix link failure without FBDEV emulation (Arnd Bergmann)
- Quirk disable panel replay on certain Dell XPS models (Jouni)
- Check if VESA DPCD AUX backlight is possible (Suraj)

Other:
- Mailmap update for Christoph (Christoph)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

# Conflicts:
#	drivers/gpu/drm/i915/display/intel_plane.c
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/ac9dfdb745d5a67c519ea150a6f36f8f74b8760e@intel.com
parents f6225b54 e012fa31

.mailmap

+1 −0
Original line number Diff line number Diff line
@@ -196,6 +196,7 @@ Christophe Leroy <chleroy@kernel.org> <christophe.leroy2@cs-soprasteria.com> 
Christophe Ricard <christophe.ricard@gmail.com>

Christopher Obbard <christopher.obbard@linaro.org> <chris.obbard@collabora.com>

Christoph Hellwig <hch@lst.de>

Christoph Manszewski <c.manszewski@gmail.com> <christoph.manszewski@intel.com>

Chuck Lever <chuck.lever@oracle.com> <cel@kernel.org>

Chuck Lever <chuck.lever@oracle.com> <cel@netapp.com>

Chuck Lever <chuck.lever@oracle.com> <cel@citi.umich.edu>

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -254,6 +254,7 @@ i915-y += \ 
	display/intel_crtc_state_dump.o \

	display/intel_cursor.o \

	display/intel_dbuf_bw.o \

	display/intel_de.o \

	display/intel_display.o \

	display/intel_display_conversion.o \

	display/intel_display_driver.o \

drivers/gpu/drm/i915/display/icl_dsi.c

+14 −7
Original line number Diff line number Diff line
@@ -711,7 +711,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 
		dsi_trans = dsi_port_to_transcoder(port);

		tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));



		if (intel_dsi->eotp_pkt)

		if (intel_dsi->eot_pkt)

			tmp &= ~EOTP_DISABLED;

		else

			tmp |= EOTP_DISABLED;
@@ -729,6 +729,12 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 
		else

			tmp |= CLK_HS_CONTINUOUS;



		if (DISPLAY_VER(display) >= 12 &&

		    intel_dsi->lp_clock_during_lpm)

			tmp |= LP_CLK_DURING_LPM;

		else

			tmp &= ~LP_CLK_DURING_LPM;



		/* configure buffer threshold limit to minimum */

		tmp &= ~PIX_BUF_THRESHOLD_MASK;

		tmp |= PIX_BUF_THRESHOLD_1_4;
@@ -765,10 +771,11 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 
			}

		}



		if (DISPLAY_VER(display) >= 12) {

			if (is_vid_mode(intel_dsi))

		if (DISPLAY_VER(display) >= 12 &&

		    is_vid_mode(intel_dsi) && intel_dsi->blanking_pkt)

			tmp |= BLANKING_PACKET_ENABLE;

		}

		else

			tmp &= ~BLANKING_PACKET_ENABLE;



		/* program DSI operation mode */

		if (is_vid_mode(intel_dsi)) {
@@ -888,7 +895,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 
	 * non-compressed link speeds, and simplifies down to the ratio between

	 * compressed and non-compressed bpp.

	 */

	if (crtc_state->dsc.compression_enable) {

	if (is_vid_mode(intel_dsi) && crtc_state->dsc.compression_enable) {

		mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);

		div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);

	}
@@ -1502,7 +1509,7 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder, 
	struct drm_display_mode *adjusted_mode =

					&pipe_config->hw.adjusted_mode;



	if (pipe_config->dsc.compressed_bpp_x16) {

	if (is_vid_mode(intel_dsi) && pipe_config->dsc.compressed_bpp_x16) {

		int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);

		int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);

drivers/gpu/drm/i915/display/icl_dsi_regs.h

+2 −1
Original line number Diff line number Diff line
@@ -227,12 +227,13 @@ 
#define  CLK_ENTER_LP_AFTER_DATA	(0x0 << 8)

#define  CLK_HS_OR_LP			(0x2 << 8)

#define  CLK_HS_CONTINUOUS		(0x3 << 8)

#define  LP_CLK_DURING_LPM		(1 << 7) /* tgl+ */

#define  LINK_CALIBRATION_MASK		(0x3 << 4)

#define  LINK_CALIBRATION_SHIFT		4

#define  CALIBRATION_DISABLED		(0x0 << 4)

#define  CALIBRATION_ENABLED_INITIAL_ONLY	(0x2 << 4)

#define  CALIBRATION_ENABLED_INITIAL_PERIODIC	(0x3 << 4)

#define  BLANKING_PACKET_ENABLE		(1 << 2)

#define  BLANKING_PACKET_ENABLE		(1 << 2) /* tgl+ */

#define  S3D_ORIENTATION_LANDSCAPE	(1 << 1)

#define  EOTP_DISABLED			(1 << 0)

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+6 −4
Original line number Diff line number Diff line
@@ -2180,7 +2180,7 @@ static int intel_c10pll_calc_state(const struct intel_crtc_state *crtc_state, 
	return 0;

}



static int readout_enabled_lane_count(struct intel_encoder *encoder)

int intel_readout_lane_count(struct intel_encoder *encoder, int lane0, int lane1)

{

	struct intel_display *display = to_intel_display(encoder);

	u8 enabled_tx_lane_count = 0;
@@ -2212,7 +2212,7 @@ static int readout_enabled_lane_count(struct intel_encoder *encoder) 
		max_tx_lane_count = round_up(max_tx_lane_count, 2);



	for (tx_lane = 0; tx_lane < max_tx_lane_count; tx_lane++) {

		u8 phy_lane_mask = tx_lane < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;

		u8 phy_lane_mask = tx_lane < 2 ? lane0 : lane1;

		int tx = tx_lane % 2 + 1;

		u8 val;
@@ -2252,7 +2252,8 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder, 
	 */

	intel_c10_msgbus_access_begin(encoder, lane);



	cx0pll_state->lane_count = readout_enabled_lane_count(encoder);

	cx0pll_state->lane_count = intel_readout_lane_count(encoder, INTEL_CX0_LANE0,

							    INTEL_CX0_LANE1);



	for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)

		pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i));
@@ -2707,7 +2708,8 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, 


	wakeref = intel_cx0_phy_transaction_begin(encoder);



	cx0pll_state->lane_count = readout_enabled_lane_count(encoder);

	cx0pll_state->lane_count = intel_readout_lane_count(encoder, INTEL_CX0_LANE0,

							    INTEL_CX0_LANE1);



	/* 1. Read VDR params and current context selection */

	intel_c20_readout_vdr_params(encoder, &pll_state->vdr, &cntx);