Commit 28ab9a02 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/mes11: remove aggregated doorbell code 



It's not enabled in hardware so the code is dead.
Remove it.

Reviewed-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 53dd920c

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+15 −71
Original line number Diff line number Diff line
@@ -5170,34 +5170,7 @@ static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 
static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)

{

	struct amdgpu_device *adev = ring->adev;

	uint32_t *wptr_saved;

	uint32_t *is_queue_unmap;

	uint64_t aggregated_db_index;

	uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size;

	uint64_t wptr_tmp;



	if (ring->is_mes_queue) {

		wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);

		is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +

					      sizeof(uint32_t));

		aggregated_db_index =

			amdgpu_mes_get_aggregated_doorbell_index(adev,

								 ring->hw_prio);



		wptr_tmp = ring->wptr & ring->buf_mask;

		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);

		*wptr_saved = wptr_tmp;

		/* assume doorbell always being used by mes mapped queue */

		if (*is_queue_unmap) {

			WDOORBELL64(aggregated_db_index, wptr_tmp);

			WDOORBELL64(ring->doorbell_index, wptr_tmp);

		} else {

			WDOORBELL64(ring->doorbell_index, wptr_tmp);



			if (*is_queue_unmap)

				WDOORBELL64(aggregated_db_index, wptr_tmp);

		}

	} else {

	if (ring->use_doorbell) {

		/* XXX check if swapping is necessary on BE */

		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
@@ -5210,7 +5183,6 @@ static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 
			     upper_32_bits(ring->wptr));

	}

}

}



static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring)

{
@@ -5233,34 +5205,7 @@ static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 
static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring)

{

	struct amdgpu_device *adev = ring->adev;

	uint32_t *wptr_saved;

	uint32_t *is_queue_unmap;

	uint64_t aggregated_db_index;

	uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size;

	uint64_t wptr_tmp;



	if (ring->is_mes_queue) {

		wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);

		is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +

					      sizeof(uint32_t));

		aggregated_db_index =

			amdgpu_mes_get_aggregated_doorbell_index(adev,

								 ring->hw_prio);



		wptr_tmp = ring->wptr & ring->buf_mask;

		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);

		*wptr_saved = wptr_tmp;

		/* assume doorbell always used by mes mapped queue */

		if (*is_queue_unmap) {

			WDOORBELL64(aggregated_db_index, wptr_tmp);

			WDOORBELL64(ring->doorbell_index, wptr_tmp);

		} else {

			WDOORBELL64(ring->doorbell_index, wptr_tmp);



			if (*is_queue_unmap)

				WDOORBELL64(aggregated_db_index, wptr_tmp);

		}

	} else {

	/* XXX check if swapping is necessary on BE */

	if (ring->use_doorbell) {

		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
@@ -5270,7 +5215,6 @@ static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 
		BUG(); /* only DOORBELL method supported on gfx11 now */

	}

}

}



static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)

{

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

+0 −56
Original line number Diff line number Diff line
@@ -414,60 +414,6 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 
			offsetof(union MESAPI_SET_HW_RESOURCES, api_status));

}



static void mes_v11_0_init_aggregated_doorbell(struct amdgpu_mes *mes)

{

	struct amdgpu_device *adev = mes->adev;

	uint32_t data;



	data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1);

	data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK |

		  CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK |

		  CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK);

	data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] <<

		CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT;

	data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT;

	WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data);



	data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2);

	data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK |

		  CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK |

		  CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK);

	data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] <<

		CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT;

	data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT;

	WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data);



	data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3);

	data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK |

		  CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK |

		  CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK);

	data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] <<

		CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT;

	data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT;

	WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data);



	data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4);

	data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK |

		  CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK |

		  CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK);

	data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] <<

		CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT;

	data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT;

	WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data);



	data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5);

	data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK |

		  CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK |

		  CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK);

	data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] <<

		CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT;

	data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT;

	WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data);



	data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT;

	WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data);

}



static const struct amdgpu_mes_funcs mes_v11_0_funcs = {

	.add_hw_queue = mes_v11_0_add_hw_queue,

	.remove_hw_queue = mes_v11_0_remove_hw_queue,
@@ -1243,8 +1189,6 @@ static int mes_v11_0_hw_init(void *handle) 
	if (r)

		goto failure;



	mes_v11_0_init_aggregated_doorbell(&adev->mes);



	r = mes_v11_0_query_sched_status(&adev->mes);

	if (r) {

		DRM_ERROR("MES is busy\n");

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

+25 −58
Original line number Diff line number Diff line
@@ -156,39 +156,7 @@ static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 
static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring)

{

	struct amdgpu_device *adev = ring->adev;

	uint32_t *wptr_saved;

	uint32_t *is_queue_unmap;

	uint64_t aggregated_db_index;

	uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size;



	DRM_DEBUG("Setting write pointer\n");



	if (ring->is_mes_queue) {

		wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);

		is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +

					      sizeof(uint32_t));

		aggregated_db_index =

			amdgpu_mes_get_aggregated_doorbell_index(adev,

							 ring->hw_prio);



		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,

			     ring->wptr << 2);

		*wptr_saved = ring->wptr << 2;

		if (*is_queue_unmap) {

			WDOORBELL64(aggregated_db_index, ring->wptr << 2);

			DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",

					ring->doorbell_index, ring->wptr << 2);

			WDOORBELL64(ring->doorbell_index, ring->wptr << 2);

		} else {

			DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",

					ring->doorbell_index, ring->wptr << 2);

			WDOORBELL64(ring->doorbell_index, ring->wptr << 2);



			if (*is_queue_unmap)

				WDOORBELL64(aggregated_db_index,

					    ring->wptr << 2);

		}

	} else {

	if (ring->use_doorbell) {

		DRM_DEBUG("Using doorbell -- "

			  "wptr_offs == 0x%08x "
@@ -219,7 +187,6 @@ static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring) 
				upper_32_bits(ring->wptr << 2));

	}

}

}



static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

{