Commit 28d47bca authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'net-stmmac-dwmac-rk-add-gmac-support-for-rk3528' 

Jonas Karlman says:

====================
net: stmmac: dwmac-rk: Add GMAC support for RK3528

The Rockchip RK3528 has two Ethernet controllers, one 100/10 MAC to be
used with the integrated PHY and a second 1000/100/10 MAC to be used
with an external Ethernet PHY.

This series add initial support for the Ethernet controllers found
in RK3528 and initial support to power up/down the integrated PHY.

v2: https://lore.kernel.org/20250309232622.1498084-1-jonas@kwiboo.se
v1: https://lore.kernel.org/20250306221402.1704196-1-jonas@kwiboo.se
====================

Link: https://patch.msgid.link/20250319214415.3086027-1-jonas@kwiboo.se


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 73ed6f53 83e7b35c

Documentation/devicetree/bindings/net/rockchip-dwmac.yaml

+15 −1
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ select: 
          - rockchip,rk3366-gmac

          - rockchip,rk3368-gmac

          - rockchip,rk3399-gmac

          - rockchip,rk3528-gmac

          - rockchip,rk3568-gmac

          - rockchip,rk3576-gmac

          - rockchip,rk3588-gmac
@@ -49,6 +50,7 @@ properties: 
              - rockchip,rv1108-gmac

      - items:

          - enum:

              - rockchip,rk3528-gmac

              - rockchip,rk3568-gmac

              - rockchip,rk3576-gmac

              - rockchip,rk3588-gmac
@@ -66,7 +68,7 @@ properties: 
      - const: eth_wake_irq



  clocks:

    minItems: 5

    minItems: 4

    maxItems: 8



  clock-names:
@@ -140,6 +142,18 @@ allOf: 
      properties:

        rockchip,php-grf: false



  - if:

      not:

        properties:

          compatible:

            contains:

              enum:

                - rockchip,rk3528-gmac

    then:

      properties:

        clocks:

          minItems: 5



unevaluatedProperties: false



examples:

drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c

+227 −50
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ struct rk_gmac_ops { 
	void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,

				    bool enable);

	void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);

	void (*integrated_phy_powerdown)(struct rk_priv_data *bsp_priv);

	bool php_grf_required;

	bool regs_valid;

	u32 regs[];
@@ -92,6 +93,76 @@ struct rk_priv_data { 
	(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \

	 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))



#define RK_GRF_MACPHY_CON0		0xb00

#define RK_GRF_MACPHY_CON1		0xb04

#define RK_GRF_MACPHY_CON2		0xb08

#define RK_GRF_MACPHY_CON3		0xb0c



#define RK_MACPHY_ENABLE		GRF_BIT(0)

#define RK_MACPHY_DISABLE		GRF_CLR_BIT(0)

#define RK_MACPHY_CFG_CLK_50M		GRF_BIT(14)

#define RK_GMAC2PHY_RMII_MODE		(GRF_BIT(6) | GRF_CLR_BIT(7))

#define RK_GRF_CON2_MACPHY_ID		HIWORD_UPDATE(0x1234, 0xffff, 0)

#define RK_GRF_CON3_MACPHY_ID		HIWORD_UPDATE(0x35, 0x3f, 0)



static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv)

{

	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);

	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);



	regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);

	regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);



	if (priv->phy_reset) {

		/* PHY needs to be disabled before trying to reset it */

		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);

		if (priv->phy_reset)

			reset_control_assert(priv->phy_reset);

		usleep_range(10, 20);

		if (priv->phy_reset)

			reset_control_deassert(priv->phy_reset);

		usleep_range(10, 20);

		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);

		msleep(30);

	}

}



static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv)

{

	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);

	if (priv->phy_reset)

		reset_control_assert(priv->phy_reset);

}



#define RK_FEPHY_SHUTDOWN		GRF_BIT(1)

#define RK_FEPHY_POWERUP		GRF_CLR_BIT(1)

#define RK_FEPHY_INTERNAL_RMII_SEL	GRF_BIT(6)

#define RK_FEPHY_24M_CLK_SEL		(GRF_BIT(8) | GRF_BIT(9))

#define RK_FEPHY_PHY_ID			GRF_BIT(11)



static void rk_gmac_integrated_fephy_powerup(struct rk_priv_data *priv,

					     unsigned int reg)

{

	reset_control_assert(priv->phy_reset);

	usleep_range(20, 30);



	regmap_write(priv->grf, reg,

		     RK_FEPHY_POWERUP |

		     RK_FEPHY_INTERNAL_RMII_SEL |

		     RK_FEPHY_24M_CLK_SEL |

		     RK_FEPHY_PHY_ID);

	usleep_range(10000, 12000);



	reset_control_deassert(priv->phy_reset);

	usleep_range(50000, 60000);

}



static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv,

					       unsigned int reg)

{

	regmap_write(priv->grf, reg, RK_FEPHY_SHUTDOWN);

}



#define PX30_GRF_GMAC_CON1		0x0904



/* PX30_GRF_GMAC_CON1 */
@@ -324,6 +395,8 @@ static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv) 
{

	regmap_write(priv->grf, RK3228_GRF_CON_MUX,

		     RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);



	rk_gmac_integrated_ephy_powerup(priv);

}



static const struct rk_gmac_ops rk3228_ops = {
@@ -332,6 +405,7 @@ static const struct rk_gmac_ops rk3228_ops = { 
	.set_rgmii_speed = rk3228_set_rgmii_speed,

	.set_rmii_speed = rk3228_set_rmii_speed,

	.integrated_phy_powerup = rk3228_integrated_phy_powerup,

	.integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,

};



#define RK3288_GRF_SOC_CON1	0x0248
@@ -557,6 +631,8 @@ static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv) 
{

	regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,

		     RK3328_MACPHY_RMII_MODE);



	rk_gmac_integrated_ephy_powerup(priv);

}



static const struct rk_gmac_ops rk3328_ops = {
@@ -565,6 +641,7 @@ static const struct rk_gmac_ops rk3328_ops = { 
	.set_rgmii_speed = rk3328_set_rgmii_speed,

	.set_rmii_speed = rk3328_set_rmii_speed,

	.integrated_phy_powerup = rk3328_integrated_phy_powerup,

	.integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,

};



#define RK3366_GRF_SOC_CON6	0x0418
@@ -828,6 +905,149 @@ static const struct rk_gmac_ops rk3399_ops = { 
	.set_rmii_speed = rk3399_set_rmii_speed,

};



#define RK3528_VO_GRF_GMAC_CON		0x0018

#define RK3528_VO_GRF_MACPHY_CON0	0x001c

#define RK3528_VO_GRF_MACPHY_CON1	0x0020

#define RK3528_VPU_GRF_GMAC_CON5	0x0018

#define RK3528_VPU_GRF_GMAC_CON6	0x001c



#define RK3528_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(15)

#define RK3528_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(15)

#define RK3528_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(14)

#define RK3528_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(14)



#define RK3528_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0xFF, 8)

#define RK3528_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0xFF, 0)



#define RK3528_GMAC0_PHY_INTF_SEL_RMII	GRF_BIT(1)

#define RK3528_GMAC1_PHY_INTF_SEL_RGMII	GRF_CLR_BIT(8)

#define RK3528_GMAC1_PHY_INTF_SEL_RMII	GRF_BIT(8)



#define RK3528_GMAC1_CLK_SELECT_CRU	GRF_CLR_BIT(12)

#define RK3528_GMAC1_CLK_SELECT_IO	GRF_BIT(12)



#define RK3528_GMAC0_CLK_RMII_DIV2	GRF_BIT(3)

#define RK3528_GMAC0_CLK_RMII_DIV20	GRF_CLR_BIT(3)

#define RK3528_GMAC1_CLK_RMII_DIV2	GRF_BIT(10)

#define RK3528_GMAC1_CLK_RMII_DIV20	GRF_CLR_BIT(10)



#define RK3528_GMAC1_CLK_RGMII_DIV1	(GRF_CLR_BIT(11) | GRF_CLR_BIT(10))

#define RK3528_GMAC1_CLK_RGMII_DIV5	(GRF_BIT(11) | GRF_BIT(10))

#define RK3528_GMAC1_CLK_RGMII_DIV50	(GRF_BIT(11) | GRF_CLR_BIT(10))



#define RK3528_GMAC0_CLK_RMII_GATE	GRF_BIT(2)

#define RK3528_GMAC0_CLK_RMII_NOGATE	GRF_CLR_BIT(2)

#define RK3528_GMAC1_CLK_RMII_GATE	GRF_BIT(9)

#define RK3528_GMAC1_CLK_RMII_NOGATE	GRF_CLR_BIT(9)



static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,

				int tx_delay, int rx_delay)

{

	regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,

		     RK3528_GMAC1_PHY_INTF_SEL_RGMII);



	regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,

		     DELAY_ENABLE(RK3528, tx_delay, rx_delay));



	regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6,

		     RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) |

		     RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));

}



static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)

{

	if (bsp_priv->id == 1)

		regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,

			     RK3528_GMAC1_PHY_INTF_SEL_RMII);

	else

		regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,

			     RK3528_GMAC0_PHY_INTF_SEL_RMII |

			     RK3528_GMAC0_CLK_RMII_DIV2);

}



static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)

{

	struct device *dev = &bsp_priv->pdev->dev;



	if (speed == 10)

		regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,

			     RK3528_GMAC1_CLK_RGMII_DIV50);

	else if (speed == 100)

		regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,

			     RK3528_GMAC1_CLK_RGMII_DIV5);

	else if (speed == 1000)

		regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,

			     RK3528_GMAC1_CLK_RGMII_DIV1);

	else

		dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);

}



static void rk3528_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)

{

	struct device *dev = &bsp_priv->pdev->dev;

	unsigned int reg, val;



	if (speed == 10)

		val = bsp_priv->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV20 :

					  RK3528_GMAC0_CLK_RMII_DIV20;

	else if (speed == 100)

		val = bsp_priv->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV2 :

					  RK3528_GMAC0_CLK_RMII_DIV2;

	else {

		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);

		return;

	}



	reg = bsp_priv->id == 1 ? RK3528_VPU_GRF_GMAC_CON5 :

				  RK3528_VO_GRF_GMAC_CON;



	regmap_write(bsp_priv->grf, reg, val);

}



static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,

				       bool input, bool enable)

{

	unsigned int val;



	if (bsp_priv->id == 1) {

		val = input ? RK3528_GMAC1_CLK_SELECT_IO :

			      RK3528_GMAC1_CLK_SELECT_CRU;

		val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :

				RK3528_GMAC1_CLK_RMII_GATE;

		regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val);

	} else {

		val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :

			       RK3528_GMAC0_CLK_RMII_GATE;

		regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, val);

	}

}



static void rk3528_integrated_phy_powerup(struct rk_priv_data *bsp_priv)

{

	rk_gmac_integrated_fephy_powerup(bsp_priv, RK3528_VO_GRF_MACPHY_CON0);

}



static void rk3528_integrated_phy_powerdown(struct rk_priv_data *bsp_priv)

{

	rk_gmac_integrated_fephy_powerdown(bsp_priv, RK3528_VO_GRF_MACPHY_CON0);

}



static const struct rk_gmac_ops rk3528_ops = {

	.set_to_rgmii = rk3528_set_to_rgmii,

	.set_to_rmii = rk3528_set_to_rmii,

	.set_rgmii_speed = rk3528_set_rgmii_speed,

	.set_rmii_speed = rk3528_set_rmii_speed,

	.set_clock_selection = rk3528_set_clock_selection,

	.integrated_phy_powerup = rk3528_integrated_phy_powerup,

	.integrated_phy_powerdown = rk3528_integrated_phy_powerdown,

	.regs_valid = true,

	.regs = {

		0xffbd0000, /* gmac0 */

		0xffbe0000, /* gmac1 */

		0x0, /* sentinel */

	},

};



#define RK3568_GRF_GMAC0_CON0		0x0380

#define RK3568_GRF_GMAC0_CON1		0x0384

#define RK3568_GRF_GMAC1_CON0		0x0388
@@ -1332,50 +1552,6 @@ static const struct rk_gmac_ops rv1126_ops = { 
	.set_rmii_speed = rv1126_set_rmii_speed,

};



#define RK_GRF_MACPHY_CON0		0xb00

#define RK_GRF_MACPHY_CON1		0xb04

#define RK_GRF_MACPHY_CON2		0xb08

#define RK_GRF_MACPHY_CON3		0xb0c



#define RK_MACPHY_ENABLE		GRF_BIT(0)

#define RK_MACPHY_DISABLE		GRF_CLR_BIT(0)

#define RK_MACPHY_CFG_CLK_50M		GRF_BIT(14)

#define RK_GMAC2PHY_RMII_MODE		(GRF_BIT(6) | GRF_CLR_BIT(7))

#define RK_GRF_CON2_MACPHY_ID		HIWORD_UPDATE(0x1234, 0xffff, 0)

#define RK_GRF_CON3_MACPHY_ID		HIWORD_UPDATE(0x35, 0x3f, 0)



static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)

{

	if (priv->ops->integrated_phy_powerup)

		priv->ops->integrated_phy_powerup(priv);



	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);

	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);



	regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);

	regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);



	if (priv->phy_reset) {

		/* PHY needs to be disabled before trying to reset it */

		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);

		if (priv->phy_reset)

			reset_control_assert(priv->phy_reset);

		usleep_range(10, 20);

		if (priv->phy_reset)

			reset_control_deassert(priv->phy_reset);

		usleep_range(10, 20);

		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);

		msleep(30);

	}

}



static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)

{

	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);

	if (priv->phy_reset)

		reset_control_assert(priv->phy_reset);

}



static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)

{

	struct rk_priv_data *bsp_priv = plat->bsp_priv;
@@ -1671,16 +1847,16 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv) 


	pm_runtime_get_sync(dev);



	if (bsp_priv->integrated_phy)

		rk_gmac_integrated_phy_powerup(bsp_priv);

	if (bsp_priv->integrated_phy && bsp_priv->ops->integrated_phy_powerup)

		bsp_priv->ops->integrated_phy_powerup(bsp_priv);



	return 0;

}



static void rk_gmac_powerdown(struct rk_priv_data *gmac)

{

	if (gmac->integrated_phy)

		rk_gmac_integrated_phy_powerdown(gmac);

	if (gmac->integrated_phy && gmac->ops->integrated_phy_powerdown)

		gmac->ops->integrated_phy_powerdown(gmac);



	pm_runtime_put_sync(&gmac->pdev->dev);
@@ -1819,6 +1995,7 @@ static const struct of_device_id rk_gmac_dwmac_match[] = { 
	{ .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },

	{ .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },

	{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },

	{ .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops },

	{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },

	{ .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops },

	{ .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },