Commit 28d4de7e authored by Perry Yuan's avatar Perry Yuan Committed by Alex Deucher
Browse files

drm/amdgpu: get rev_id from strap register or IP-discovery table 



Query the sub-revision field in the IP Discovery table for the VFs
to obtain their revision ID.
Meanwhile, read the revision ID from the strap register for the PF.

Signed-off-by: default avatarPerry Yuan <perry.yuan@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent edddaada

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+4 −0
Original line number Diff line number Diff line
@@ -1843,6 +1843,10 @@ static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) 
	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))

		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E;



	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) &&

		adev->rev_id == 0x3)

		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E;



	if (!(adev->flags & AMD_IS_APU) && !amdgpu_sriov_vf(adev)) {

		vram_info = RREG32(regBIF_BIOS_SCRATCH_4);

		adev->gmc.vram_vendor = vram_info & 0xF;

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

+13 −11
Original line number Diff line number Diff line
@@ -41,19 +41,21 @@ static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev) 


static u32 nbio_v7_9_get_rev_id(struct amdgpu_device *adev)

{

	u32 tmp;



	tmp = IP_VERSION_SUBREV(amdgpu_ip_version_full(adev, NBIO_HWIP, 0));

	/* If it is VF or subrevision holds a non-zero value, that should be used */

	if (tmp || amdgpu_sriov_vf(adev))

		return tmp;

	u32 rev_id;



	/* If discovery subrev is not updated, use register version */

	tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);

	tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0,

	/*

	 * fetch the sub-revision field from the IP-discovery table

	 * (returns zero if the table entry is not populated).

	 */

	if (amdgpu_sriov_vf(adev)) {

		rev_id = IP_VERSION_SUBREV(amdgpu_ip_version_full(adev, NBIO_HWIP, 0));

	} else {

		rev_id = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);

		rev_id = REG_GET_FIELD(rev_id, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0,

				STRAP_ATI_REV_ID_DEV0_F0);

	}



	return tmp;

	return rev_id;

}



static void nbio_v7_9_mc_access_enable(struct amdgpu_device *adev, bool enable)