Commit 28e7241c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips_6.11_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 

Pull MIPS updates from Thomas Bogendoerfer:

 - Use improved timer sync for Loongson64

 - Fix address of GCR_ACCESS register

 - Add missing MODULE_DESCRIPTION

* tag 'mips_6.11_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  mips: sibyte: add missing MODULE_DESCRIPTION() macro
  MIPS: SMP-CPS: Fix address for GCR_ACCESS register for CM3 and later
  MIPS: Loongson64: Switch to SYNC_R4K
parents f6464295 2c716cf1

arch/mips/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -478,6 +478,7 @@ config MACH_LOONGSON64 
	select BOARD_SCACHE

	select CSRC_R4K

	select CEVT_R4K

	select SYNC_R4K

	select FORCE_PCI

	select ISA

	select I8259

arch/mips/include/asm/mips-cm.h

+4 −0
Original line number Diff line number Diff line
@@ -240,6 +240,10 @@ GCR_ACCESSOR_RO(32, 0x0d0, gic_status) 
GCR_ACCESSOR_RO(32, 0x0f0, cpc_status)

#define CM_GCR_CPC_STATUS_EX			BIT(0)



/* GCR_ACCESS - Controls core/IOCU access to GCRs */

GCR_ACCESSOR_RW(32, 0x120, access_cm3)

#define CM_GCR_ACCESS_ACCESSEN			GENMASK(7, 0)



/* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */

GCR_ACCESSOR_RW(32, 0x130, l2_config)

#define CM_GCR_L2_CONFIG_BYPASS			BIT(20)

arch/mips/include/asm/smp.h

+0 −1
Original line number Diff line number Diff line
@@ -50,7 +50,6 @@ extern int __cpu_logical_map[NR_CPUS]; 
#define SMP_CALL_FUNCTION	0x2

/* Octeon - Tell another core to flush its icache */

#define SMP_ICACHE_FLUSH	0x4

#define SMP_ASK_C0COUNT		0x8



/* Mask of CPUs which are currently definitely operating coherently */

extern cpumask_t cpu_coherent_mask;

arch/mips/kernel/smp-cps.c

+4 −1
Original line number Diff line number Diff line
@@ -317,7 +317,10 @@ static void boot_core(unsigned int core, unsigned int vpe_id) 
	write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB);



	/* Ensure the core can access the GCRs */

	if (mips_cm_revision() < CM_REV_CM3)

		set_gcr_access(1 << core);

	else

		set_gcr_access_cm3(1 << core);



	if (mips_cpc_present()) {

		/* Reset the core */

arch/mips/loongson64/smp.c

+2 −33
Original line number Diff line number Diff line
@@ -33,7 +33,6 @@ static void __iomem *ipi_clear0_regs[16]; 
static void __iomem *ipi_status0_regs[16];

static void __iomem *ipi_en0_regs[16];

static void __iomem *ipi_mailbox_buf[16];

static uint32_t core0_c0count[NR_CPUS];



static u32 (*ipi_read_clear)(int cpu);

static void (*ipi_write_action)(int cpu, u32 action);
@@ -382,11 +381,10 @@ loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action) 
		ipi_write_action(cpu_logical_map(i), (u32)action);

}





static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id)

{

	int i, cpu = smp_processor_id();

	unsigned int action, c0count;

	int cpu = smp_processor_id();

	unsigned int action;



	action = ipi_read_clear(cpu);
@@ -399,26 +397,14 @@ static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id) 
		irq_exit();

	}



	if (action & SMP_ASK_C0COUNT) {

		BUG_ON(cpu != 0);

		c0count = read_c0_count();

		c0count = c0count ? c0count : 1;

		for (i = 1; i < nr_cpu_ids; i++)

			core0_c0count[i] = c0count;

		nudge_writes(); /* Let others see the result ASAP */

	}



	return IRQ_HANDLED;

}



#define MAX_LOOPS 800

/*

 * SMP init and finish on secondary CPUs

 */

static void loongson3_init_secondary(void)

{

	int i;

	uint32_t initcount;

	unsigned int cpu = smp_processor_id();

	unsigned int imask = STATUSF_IP7 | STATUSF_IP6 |

			     STATUSF_IP3 | STATUSF_IP2;
@@ -432,23 +418,6 @@ static void loongson3_init_secondary(void) 
		     cpu_logical_map(cpu) % loongson_sysconf.cores_per_package);

	cpu_data[cpu].package =

		cpu_logical_map(cpu) / loongson_sysconf.cores_per_package;



	i = 0;

	core0_c0count[cpu] = 0;

	loongson3_send_ipi_single(0, SMP_ASK_C0COUNT);

	while (!core0_c0count[cpu]) {

		i++;

		cpu_relax();

	}



	if (i > MAX_LOOPS)

		i = MAX_LOOPS;

	if (cpu_data[cpu].package)

		initcount = core0_c0count[cpu] + i;

	else /* Local access is faster for loops */

		initcount = core0_c0count[cpu] + i/2;



	write_c0_count(initcount);

}



static void loongson3_smp_finish(void)