Commit 29521343 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.7-tag1' of... 

Merge tag 'renesas-clk-for-v6.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v6.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a7795: Constify r8a7795_*_clks
  clk: renesas: r9a06g032: Name anonymous structs
  clk: renesas: r9a06g032: Fix kerneldoc warning
  clk: renesas: rzg2l: Use u32 for flag and mux_flags
  clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields
  clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable()
  clk: renesas: rzg2l: Use core->name for clock name
  clk: renesas: r9a06g032: Use for_each_compatible_node()
parents 0bb80ecc 87882525

drivers/clk/renesas/r8a7795-cpg-mssr.c

+2 −2
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ enum clk_ids { 
	MOD_CLK_BASE

};



static struct cpg_core_clk r8a7795_core_clks[] __initdata = {

static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {

	/* External Clock Inputs */

	DEF_INPUT("extal",      CLK_EXTAL),

	DEF_INPUT("extalr",     CLK_EXTALR),
@@ -128,7 +128,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { 
	DEF_BASE("r",           R8A7795_CLK_R,     CLK_TYPE_GEN3_R, CLK_RINT),

};



static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {

static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {

	DEF_MOD("3dge",			 112,	R8A7795_CLK_ZG),

	DEF_MOD("fdp1-1",		 118,	R8A7795_CLK_S0D1),

	DEF_MOD("fdp1-0",		 119,	R8A7795_CLK_S0D1),

drivers/clk/renesas/r9a06g032-clocks.c

+36 −33
Original line number Diff line number Diff line
@@ -102,19 +102,22 @@ enum gate_type { 
 * @source:    the ID+1 of the parent clock element.

 *             Root clock uses ID of ~0 (PARENT_ID);

 * @gate:      clock enable/disable

 * @div_min:   smallest permitted clock divider

 * @div_max:   largest permitted clock divider

 * @reg:       clock divider register offset, in 32-bit words

 * @div_table: optional list of fixed clock divider values;

 * @div:       substructure for clock divider

 * @div.min:   smallest permitted clock divider

 * @div.max:   largest permitted clock divider

 * @div.reg:   clock divider register offset, in 32-bit words

 * @div.table: optional list of fixed clock divider values;

 *             must be in ascending order, zero for unused

 * @div:       divisor for fixed-factor clock

 * @mul:       multiplier for fixed-factor clock

 * @group:     UART group, 0=UART0/1/2, 1=UART3/4/5/6/7

 * @sel:       select either g1/r1 or g2/r2 as clock source

 * @g1:        1st source gate (clock enable/disable)

 * @r1:        1st source reset (module reset)

 * @g2:        2nd source gate (clock enable/disable)

 * @r2:        2nd source reset (module reset)

 * @ffc:       substructure for fixed-factor clocks

 * @ffc.div:   divisor for fixed-factor clock

 * @ffc.mul:   multiplier for fixed-factor clock

 * @dual:      substructure for dual clock gates

 * @dual.group: UART group, 0=UART0/1/2, 1=UART3/4/5/6/7

 * @dual.sel:  select either g1/r1 or g2/r2 as clock source

 * @dual.g1:   1st source gate (clock enable/disable)

 * @dual.r1:   1st source reset (module reset)

 * @dual.g2:   2nd source gate (clock enable/disable)

 * @dual.r2:   2nd source reset (module reset)

 *

 * Describes a single element in the clock tree hierarchy.

 * As there are quite a large number of clock elements, this
@@ -131,13 +134,13 @@ struct r9a06g032_clkdesc { 
		struct r9a06g032_gate gate;

		/* type = K_DIV  */

		struct {

			unsigned int div_min:10, div_max:10, reg:10;

			u16 div_table[4];

		};

			unsigned int min:10, max:10, reg:10;

			u16 table[4];

		} div;

		/* type = K_FFC */

		struct {

			u16 div, mul;

		};

		} ffc;

		/* type = K_DUALGATE */

		struct {

			uint16_t group:1;
@@ -178,26 +181,26 @@ struct r9a06g032_clkdesc { 
	.type = K_FFC, \

	.index = R9A06G032_##_idx, \

	.name = _n, \

	.div = _div, \

	.mul = _mul \

	.ffc.div = _div, \

	.ffc.mul = _mul \

}

#define D_FFC(_idx, _n, _src, _div) { \

	.type = K_FFC, \

	.index = R9A06G032_##_idx, \

	.source = 1 + R9A06G032_##_src, \

	.name = _n, \

	.div = _div, \

	.mul = 1 \

	.ffc.div = _div, \

	.ffc.mul = 1 \

}

#define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) { \

	.type = K_DIV, \

	.index = R9A06G032_##_idx, \

	.source = 1 + R9A06G032_##_src, \

	.name = _n, \

	.reg = _reg, \

	.div_min = _min, \

	.div_max = _max, \

	.div_table = { __VA_ARGS__ } \

	.div.reg = _reg, \

	.div.min = _min, \

	.div.max = _max, \

	.div.table = { __VA_ARGS__ } \

}

#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) { \

	.type = K_DUALGATE, \
@@ -1063,14 +1066,14 @@ r9a06g032_register_div(struct r9a06g032_priv *clocks, 


	div->clocks = clocks;

	div->index = desc->index;

	div->reg = desc->reg;

	div->reg = desc->div.reg;

	div->hw.init = &init;

	div->min = desc->div_min;

	div->max = desc->div_max;

	div->min = desc->div.min;

	div->max = desc->div.max;

	/* populate (optional) divider table fixed values */

	for (i = 0; i < ARRAY_SIZE(div->table) &&

	     i < ARRAY_SIZE(desc->div_table) && desc->div_table[i]; i++) {

		div->table[div->table_size++] = desc->div_table[i];

	     i < ARRAY_SIZE(desc->div.table) && desc->div.table[i]; i++) {

		div->table[div->table_size++] = desc->div.table[i];

	}



	clk = clk_register(NULL, &div->hw);
@@ -1269,11 +1272,10 @@ static void r9a06g032_clocks_del_clk_provider(void *data) 


static void __init r9a06g032_init_h2mode(struct r9a06g032_priv *clocks)

{

	struct device_node *usbf_np = NULL;

	struct device_node *usbf_np;

	u32 usb;



	while ((usbf_np = of_find_compatible_node(usbf_np, NULL,

						  "renesas,rzn1-usbf"))) {

	for_each_compatible_node(usbf_np, NULL, "renesas,rzn1-usbf") {

		if (of_device_is_available(usbf_np))

			break;

	}
@@ -1333,7 +1335,8 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev) 
		case K_FFC:

			clk = clk_register_fixed_factor(NULL, d->name,

							parent_name, 0,

							d->mul, d->div);

							d->ffc.mul,

							d->ffc.div);

			break;

		case K_GATE:

			clk = r9a06g032_register_gate(clocks, parent_name, d);

drivers/clk/renesas/rzg2l-cpg.c

+8 −9
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
 * Copyright (C) 2015 Renesas Electronics Corp.

 */



#include <linux/bitfield.h>

#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/clk/renesas.h>
@@ -38,14 +39,13 @@ 
#define WARN_DEBUG(x)	do { } while (0)

#endif



#define DIV_RSMASK(v, s, m)	((v >> s) & m)

#define GET_SHIFT(val)		((val >> 12) & 0xff)

#define GET_WIDTH(val)		((val >> 8) & 0xf)



#define KDIV(val)		DIV_RSMASK(val, 16, 0xffff)

#define MDIV(val)		DIV_RSMASK(val, 6, 0x3ff)

#define PDIV(val)		DIV_RSMASK(val, 0, 0x3f)

#define SDIV(val)		DIV_RSMASK(val, 0, 0x7)

#define KDIV(val)		FIELD_GET(GENMASK(31, 16), val)

#define MDIV(val)		FIELD_GET(GENMASK(15, 6), val)

#define PDIV(val)		FIELD_GET(GENMASK(5, 0), val)

#define SDIV(val)		FIELD_GET(GENMASK(2, 0), val)



#define CLK_ON_R(reg)		(reg)

#define CLK_MON_R(reg)		(0x180 + (reg))
@@ -265,7 +265,7 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core, 
	clk_hw_data->priv = priv;

	clk_hw_data->conf = core->conf;



	init.name = GET_SHIFT(core->conf) ? "sd1" : "sd0";

	init.name = core->name;

	init.ops = &rzg2l_cpg_sd_clk_mux_ops;

	init.flags = 0;

	init.num_parents = core->num_parents;
@@ -909,10 +909,9 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) 
		enable ? "ON" : "OFF");

	spin_lock_irqsave(&priv->rmw_lock, flags);



	if (enable)

		value = (bitmask << 16) | bitmask;

	else

	value = bitmask << 16;

	if (enable)

		value |= bitmask;

	writel(value, priv->base + CLK_ON_R(reg));



	spin_unlock_irqrestore(&priv->rmw_lock, flags);

drivers/clk/renesas/rzg2l-cpg.h

+2 −2
Original line number Diff line number Diff line
@@ -92,8 +92,8 @@ struct cpg_core_clk { 
	unsigned int conf;

	const struct clk_div_table *dtable;

	const char * const *parent_names;

	int flag;

	int mux_flags;

	u32 flag;

	u32 mux_flags;

	int num_parents;

};