Commit 29654910 authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Rodrigo Vivi
Browse files

drm/xe: base definitions for the GSCCS 



The first step in introducing the GSCCS is to add all the basic defs for
it (name, mmio base, class/instance, lrc size etc).

Bspec: 60149, 60421, 63752
Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230817201831.1583172-3-daniele.ceraolospurio@intel.com


Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 0b1d1473

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -376,6 +376,7 @@ 
#define   INTR_ENGINE_CLASS(x)			REG_FIELD_GET(GENMASK(18, 16), x)

#define   INTR_ENGINE_INTR(x)			REG_FIELD_GET(GENMASK(15, 0), x)

#define   OTHER_GUC_INSTANCE			0

#define   OTHER_GSC_INSTANCE			6



#define RENDER_COPY_INTR_ENABLE			XE_REG(0x190030)

#define VCS_VECS_INTR_ENABLE			XE_REG(0x190034)

drivers/gpu/drm/xe/regs/xe_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ 
#define XEHPC_BCS6_RING_BASE			0x3ea000

#define XEHPC_BCS7_RING_BASE			0x3ec000

#define XEHPC_BCS8_RING_BASE			0x3ee000

#define GSCCS_RING_BASE				0x11a000

#define   GT_WAIT_SEMAPHORE_INTERRUPT		REG_BIT(11)

#define   GT_CONTEXT_SWITCH_INTERRUPT		REG_BIT(8)

#define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	REG_BIT(4)

drivers/gpu/drm/xe/xe_exec_queue.c

+3 −0
Original line number Diff line number Diff line
@@ -195,6 +195,9 @@ void xe_exec_queue_assign_name(struct xe_exec_queue *q, u32 instance) 
	case XE_ENGINE_CLASS_COMPUTE:

		sprintf(q->name, "ccs%d", instance);

		break;

	case XE_ENGINE_CLASS_OTHER:

		sprintf(q->name, "gsccs%d", instance);

		break;

	default:

		XE_WARN_ON(q->class);

	}

drivers/gpu/drm/xe/xe_guc.h

+1 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ static inline u16 xe_engine_class_to_guc_class(enum xe_engine_class class) 
	case XE_ENGINE_CLASS_COMPUTE:

		return GUC_COMPUTE_CLASS;

	case XE_ENGINE_CLASS_OTHER:

		return GUC_GSC_OTHER_CLASS;

	default:

		XE_WARN_ON(class);

		return -1;

drivers/gpu/drm/xe/xe_guc_ads.c

+2 −6
Original line number Diff line number Diff line
@@ -253,9 +253,6 @@ static size_t calculate_golden_lrc_size(struct xe_guc_ads *ads) 
	int class;



	for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {

		if (class == XE_ENGINE_CLASS_OTHER)

			continue;



		if (!engine_enable_mask(gt, class))

			continue;
@@ -350,6 +347,8 @@ static void fill_engine_enable_masks(struct xe_gt *gt, 
		       engine_enable_mask(gt, XE_ENGINE_CLASS_VIDEO_ENHANCE));

	info_map_write(xe, info_map, engine_enabled_masks[GUC_COMPUTE_CLASS],

		       engine_enable_mask(gt, XE_ENGINE_CLASS_COMPUTE));

	info_map_write(xe, info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS],

		       engine_enable_mask(gt, XE_ENGINE_CLASS_OTHER));

}



static void guc_prep_golden_lrc_null(struct xe_guc_ads *ads)
@@ -638,9 +637,6 @@ static void guc_populate_golden_lrc(struct xe_guc_ads *ads) 
	for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {

		u8 guc_class;



		if (class == XE_ENGINE_CLASS_OTHER)

			continue;



		guc_class = xe_engine_class_to_guc_class(class);



		if (!info_map_read(xe, &info_map,