Commit 298ffd53 authored by Borislav Petkov (AMD)'s avatar Borislav Petkov (AMD)
Browse files

Merge remote-tracking branches 'ras/edac-cxl', 'ras/edac-drivers' and... 


Merge remote-tracking branches 'ras/edac-cxl', 'ras/edac-drivers' and 'ras/edac-misc' into edac-updates

* ras/edac-cxl:
  EDAC/device: Fix dev_set_name() format string
  EDAC: Update memory repair control interface for memory sparing feature
  EDAC: Add a memory repair control feature
  EDAC: Add a Error Check Scrub control feature
  EDAC: Add scrub control feature
  EDAC: Add support for EDAC device features control

* ras/edac-drivers:
  EDAC/ie31200: Switch Raptor Lake-S to interrupt mode
  EDAC/ie31200: Add Intel Raptor Lake-S SoCs support
  EDAC/ie31200: Break up ie31200_probe1()
  EDAC/ie31200: Fold the two channel loops into one loop
  EDAC/ie31200: Make struct dimm_data contain decoded information
  EDAC/ie31200: Make the memory controller resources configurable
  EDAC/ie31200: Simplify the pci_device_id table
  EDAC/ie31200: Fix the 3rd parameter name of *populate_dimm_info()
  EDAC/ie31200: Fix the error path order of ie31200_init()
  EDAC/ie31200: Fix the DIMM size mask for several SoCs
  EDAC/ie31200: Fix the size of EDAC_MC_LAYER_CHIP_SELECT layer
  EDAC/{skx_common,i10nm}: Fix some missing error reports on Emerald Rapids
  EDAC/igen6: Fix the flood of invalid error reports
  EDAC/ie31200: work around false positive build warning

* ras/edac-misc:
  MAINTAINERS: Add a secondary maintainer for bluefield_edac
  EDAC/pnd2: Make read-only const array intlv static
  EDAC/igen6: Constify struct res_config
  EDAC/amd64: Simplify return statement in dct_ecc_enabled()
  EDAC: Use string choice helper functions

Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
parents 49472722 a5db1b29 f30dab9d

MAINTAINERS

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@@ -8214,6 +8214,7 @@ F: drivers/edac/aspeed_edac.c 








EDAC-BLUEFIELD









M:	Shravan Kumar Ramani <shravankr@nvidia.com>









M:	David Thompson <davthompson@nvidia.com>









S:	Supported









F:	drivers/edac/bluefield_edac.c








































drivers/edac/Kconfig



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−1






























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@@ -196,7 +196,7 @@ config EDAC_I3200

















config EDAC_IE31200









	tristate "Intel e312xx"









	depends on PCI && X86









	depends on PCI && X86 && X86_MCE_INTEL









	help









	  Support for error detection and correction on the Intel









	  E3-1200 based DRAM controllers.
































drivers/edac/amd64_edac.c



+24
−28






























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// SPDX-License-Identifier: GPL-2.0-only









#include <linux/ras.h>









#include <linux/string_choices.h>









#include "amd64_edac.h"









#include <asm/amd_nb.h>









#include <asm/amd_node.h>








@@ -1171,22 +1172,21 @@ static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan)







		edac_dbg(1, " LRDIMM %dx rank multiply\n", (dcsm & 0x3));









	}



















	edac_dbg(1, "All DIMMs support ECC:%s\n",









		    (dclr & BIT(19)) ? "yes" : "no");









	edac_dbg(1, "All DIMMs support ECC: %s\n", str_yes_no(dclr & BIT(19)));





























	edac_dbg(1, "  PAR/ERR parity: %s\n",









		 (dclr & BIT(8)) ?  "enabled" : "disabled");









		 str_enabled_disabled(dclr & BIT(8)));



















	if (pvt->fam == 0x10)









		edac_dbg(1, "  DCT 128bit mode width: %s\n",









			 (dclr & BIT(11)) ?  "128b" : "64b");



















	edac_dbg(1, "  x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",









		 (dclr & BIT(12)) ?  "yes" : "no",









		 (dclr & BIT(13)) ?  "yes" : "no",









		 (dclr & BIT(14)) ?  "yes" : "no",









		 (dclr & BIT(15)) ?  "yes" : "no");









		 str_yes_no(dclr & BIT(12)),









		 str_yes_no(dclr & BIT(13)),









		 str_yes_no(dclr & BIT(14)),









		 str_yes_no(dclr & BIT(15)));









}



















#define CS_EVEN_PRIMARY		BIT(0)








@@ -1353,14 +1353,14 @@ static void umc_dump_misc_regs(struct amd64_pvt *pvt)







		edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi);



















		edac_dbg(1, "UMC%d ECC capable: %s, ChipKill ECC capable: %s\n",









				i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no",









				    (umc->umc_cap_hi & BIT(31)) ? "yes" : "no");









				i, str_yes_no(umc->umc_cap_hi & BIT(30)),









				    str_yes_no(umc->umc_cap_hi & BIT(31)));









		edac_dbg(1, "UMC%d All DIMMs support ECC: %s\n",









				i, (umc->umc_cfg & BIT(12)) ? "yes" : "no");









				i, str_yes_no(umc->umc_cfg & BIT(12)));









		edac_dbg(1, "UMC%d x4 DIMMs present: %s\n",









				i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no");









				i, str_yes_no(umc->dimm_cfg & BIT(6)));









		edac_dbg(1, "UMC%d x16 DIMMs present: %s\n",









				i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no");









				i, str_yes_no(umc->dimm_cfg & BIT(7)));



















		umc_debug_display_dimm_sizes(pvt, i);









	}








@@ -1371,11 +1371,11 @@ static void dct_dump_misc_regs(struct amd64_pvt *pvt)







	edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);



















	edac_dbg(1, "  NB two channel DRAM capable: %s\n",









		 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no");









		 str_yes_no(pvt->nbcap & NBCAP_DCT_DUAL));



















	edac_dbg(1, "  ECC capable: %s, ChipKill ECC capable: %s\n",









		 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no",









		 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no");









		 str_yes_no(pvt->nbcap & NBCAP_SECDED),









		 str_yes_no(pvt->nbcap & NBCAP_CHIPKILL));



















	debug_dump_dramcfg_low(pvt, pvt->dclr0, 0);


















@@ -1398,7 +1398,7 @@ static void dct_dump_misc_regs(struct amd64_pvt *pvt)







	if (!dct_ganging_enabled(pvt))









		debug_dump_dramcfg_low(pvt, pvt->dclr1, 1);



















	edac_dbg(1, "  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");









	edac_dbg(1, "  DramHoleValid: %s\n", str_yes_no(dhar_valid(pvt)));



















	amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz);









}








@@ -2027,15 +2027,15 @@ static void read_dram_ctl_register(struct amd64_pvt *pvt)

















		if (!dct_ganging_enabled(pvt))









			edac_dbg(0, "  Address range split per DCT: %s\n",









				 (dct_high_range_enabled(pvt) ? "yes" : "no"));









				 str_yes_no(dct_high_range_enabled(pvt)));



















		edac_dbg(0, "  data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n",









			 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"),









			 (dct_memory_cleared(pvt) ? "yes" : "no"));









			 str_enabled_disabled(dct_data_intlv_enabled(pvt)),









			 str_yes_no(dct_memory_cleared(pvt)));



















		edac_dbg(0, "  channel interleave: %s, "









			 "interleave bits selector: 0x%x\n",









			 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"),









			 str_enabled_disabled(dct_interleave_enabled(pvt)),









			 dct_sel_interleave_addr(pvt));









	}


















@@ -3208,8 +3208,7 @@ static bool nb_mce_bank_enabled_on_node(u16 nid)







		nbe = reg->l & MSR_MCGCTL_NBE;



















		edac_dbg(0, "core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",









			 cpu, reg->q,









			 (nbe ? "enabled" : "disabled"));









			 cpu, reg->q, str_enabled_disabled(nbe));



















		if (!nbe)









			goto out;








@@ -3353,12 +3352,9 @@ static bool dct_ecc_enabled(struct amd64_pvt *pvt)







		edac_dbg(0, "NB MCE bank disabled, set MSR 0x%08x[4] on node %d to enable.\n",









			 MSR_IA32_MCG_CTL, nid);



















	edac_dbg(3, "Node %d: DRAM ECC %s.\n", nid, (ecc_en ? "enabled" : "disabled"));









	edac_dbg(3, "Node %d: DRAM ECC %s.\n", nid, str_enabled_disabled(ecc_en));



















	if (!ecc_en || !nb_mce_en)









		return false;









	else









		return true;









	return ecc_en && nb_mce_en;









}



















static bool umc_ecc_enabled(struct amd64_pvt *pvt)








@@ -3378,7 +3374,7 @@ static bool umc_ecc_enabled(struct amd64_pvt *pvt)







		}









	}



















	edac_dbg(3, "Node %d: DRAM ECC %s.\n", pvt->mc_node_id, (ecc_en ? "enabled" : "disabled"));









	edac_dbg(3, "Node %d: DRAM ECC %s.\n", pvt->mc_node_id, str_enabled_disabled(ecc_en));



















	return ecc_en;









}
































drivers/edac/debugfs.c



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// SPDX-License-Identifier: GPL-2.0-only



















#include <linux/string_choices.h>



















#include "edac_module.h"



















static struct dentry *edac_debugfs;








@@ -22,7 +25,7 @@ static ssize_t edac_fake_inject_write(struct file *file,







	       "Generating %d %s fake error%s to %d.%d.%d to test core handling. NOTE: this won't test the driver-specific decoding logic.\n",









		errcount,









		(type == HW_EVENT_ERR_UNCORRECTED) ? "UE" : "CE",









		errcount > 1 ? "s" : "",









		str_plural(errcount),









		mci->fake_inject_layer[0],









		mci->fake_inject_layer[1],









		mci->fake_inject_layer[2]
































drivers/edac/i10nm_base.c



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@@ -751,6 +751,8 @@ static int i10nm_get_ddr_munits(void)







				continue;









			} else {









				d->imc[lmc].mdev = mdev;









				if (res_cfg->type == SPR)









					skx_set_mc_mapping(d, i, lmc);









				lmc++;









			}









		}