Unverified Commit 2995b503 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'v5.14-rockchip-dts32-2' of... 

Merge tag 'v5.14-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

Nodes for the Hantro-based video codecs on
rk3036, rk3066, rk3188 and rk322x.

* tag 'v5.14-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: add vpu and vdec node for RK322x
  ARM: dts: rockchip: add vpu nodes for RK3066 and RK3188
  ARM: dts: rockchip: add vpu node for RK3036

Link: https://lore.kernel.org/r/4611716.rnzMqkiUVr@diego


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents c21cc3d8 36e9534d

arch/arm/boot/dts/rk3036.dtsi

+21 −0
Original line number Diff line number Diff line
@@ -117,6 +117,27 @@ gpu: gpu@10090000 { 
		status = "disabled";

	};



	vpu: video-codec@10108000 {

		compatible = "rockchip,rk3036-vpu";

		reg = <0x10108000 0x800>;

		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "vdpu";

		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;

		clock-names = "aclk", "hclk";

		iommus = <&vpu_mmu>;

		power-domains = <&power RK3036_PD_VPU>;

	};



	vpu_mmu: iommu@10108800 {

		compatible = "rockchip,iommu";

		reg = <0x10108800 0x100>;

		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;

		clock-names = "aclk", "iface";

		power-domains = <&power RK3036_PD_VPU>;

		#iommu-cells = <0>;

	};



	vop: vop@10118000 {

		compatible = "rockchip,rk3036-vop";

		reg = <0x10118000 0x19c>;

arch/arm/boot/dts/rk3066a.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -868,6 +868,10 @@ &uart3 { 
	pinctrl-0 = <&uart3_xfer>;

};



&vpu {

	power-domains = <&power RK3066_PD_VIDEO>;

};



&wdt {

	compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";

};

arch/arm/boot/dts/rk3188.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -801,6 +801,11 @@ &uart3 { 
	pinctrl-0 = <&uart3_xfer>;

};



&vpu {

	compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu";

	power-domains = <&power RK3188_PD_VIDEO>;

};



&wdt {

	compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";

};

arch/arm/boot/dts/rk322x.dtsi

+25 −2
Original line number Diff line number Diff line
@@ -610,6 +610,18 @@ gpu: gpu@20000000 { 
		status = "disabled";

	};



	vpu: video-codec@20020000 {

		compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu";

		reg = <0x20020000 0x800>;

		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "vepu", "vdpu";

		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;

		clock-names = "aclk", "hclk";

		iommus = <&vpu_mmu>;

		power-domains = <&power RK3228_PD_VPU>;

	};



	vpu_mmu: iommu@20020800 {

		compatible = "rockchip,iommu";

		reg = <0x20020800 0x100>;
@@ -618,7 +630,19 @@ vpu_mmu: iommu@20020800 { 
		clock-names = "aclk", "iface";

		power-domains = <&power RK3228_PD_VPU>;

		#iommu-cells = <0>;

		status = "disabled";

	};



	vdec: video-codec@20030000 {

		compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec";

		reg = <0x20030000 0x480>;

		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,

			 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;

		clock-names = "axi", "ahb", "cabac", "core";

		assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;

		assigned-clock-rates = <300000000>, <300000000>;

		iommus = <&vdec_mmu>;

		power-domains = <&power RK3228_PD_RKVDEC>;

	};



	vdec_mmu: iommu@20030480 {
@@ -629,7 +653,6 @@ vdec_mmu: iommu@20030480 { 
		clock-names = "aclk", "iface";

		power-domains = <&power RK3228_PD_RKVDEC>;

		#iommu-cells = <0>;

		status = "disabled";

	};



	vop: vop@20050000 {

arch/arm/boot/dts/rk3xxx.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -47,6 +47,18 @@ gpu: gpu@10090000 { 
		status = "disabled";

	};



	vpu: video-codec@10104000 {

		compatible = "rockchip,rk3066-vpu";

		reg = <0x10104000 0x800>;

		interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "vepu", "vdpu";

		clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,

			 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;

		clock-names = "aclk_vdpu", "hclk_vdpu",

			      "aclk_vepu", "hclk_vepu";

	};



	L2: cache-controller@10138000 {

		compatible = "arm,pl310-cache";

		reg = <0x10138000 0x1000>;