Commit 2998bccf authored by Samson Tam's avatar Samson Tam Committed by Alex Deucher
Browse files

drm/amd/display: Enable ISHARP support for DCN401 



[Why]
Enable sharpener support for DCN401

[How]
- Removed memcmp check that was preventing ISHARP from being enabled.
- Add missing ISHARP register defines, masks, and writes.
- Add programming of Blur and Scale coefficients.
- Program FMT_MODE and NLDELTA registers based on LLS_PREF and pixel
- format
- Only enable ISHARP for YUV420
- Add disabling of ISHARP
- Add debug flags and registry keys for debugging ISHARP.
- Set default to medium level

Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarSamson Tam <Samson.Tam@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c2edec16

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -1040,6 +1040,7 @@ struct dc_debug_options { 
	unsigned int force_cositing;

	unsigned int disable_spl;

	unsigned int force_easf;

	unsigned int force_sharpness;

	unsigned int force_lls;

};

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

+19 −10
Original line number Diff line number Diff line
@@ -134,15 +134,24 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl 
		spl_in->prefer_easf = false;

	else if (pipe_ctx->stream->ctx->dc->debug.force_easf == 2)

		spl_in->disable_easf = true;

	// Translate adaptive sharpening preference

	/* Translate adaptive sharpening preference */

	if (pipe_ctx->stream->ctx->dc->debug.force_sharpness > 0) {

		spl_in->adaptive_sharpness.enable = (pipe_ctx->stream->ctx->dc->debug.force_sharpness > 1) ? true : false;

		if (pipe_ctx->stream->ctx->dc->debug.force_sharpness == 2)

			spl_in->adaptive_sharpness.sharpness = SHARPNESS_LOW;

		else if (pipe_ctx->stream->ctx->dc->debug.force_sharpness == 3)

			spl_in->adaptive_sharpness.sharpness = SHARPNESS_MID;

		else if (pipe_ctx->stream->ctx->dc->debug.force_sharpness >= 4)

			spl_in->adaptive_sharpness.sharpness = SHARPNESS_HIGH;

	} else {

		spl_in->adaptive_sharpness.enable = plane_state->adaptive_sharpness_en;

	if (plane_state->sharpnessX1000 == 0)	{

		if (plane_state->sharpnessX1000 == 0)

			spl_in->adaptive_sharpness.enable = false;

	} else if (plane_state->sharpnessX1000 < 999)	{

		else if (plane_state->sharpnessX1000 < 999)

			spl_in->adaptive_sharpness.sharpness = SHARPNESS_LOW;

	} else if (plane_state->sharpnessX1000 < 1999)	{

		else if (plane_state->sharpnessX1000 < 1999)

			spl_in->adaptive_sharpness.sharpness = SHARPNESS_MID;

	} else	{	// Any other value is high sharpness

		else // Any other value is high sharpness

			spl_in->adaptive_sharpness.sharpness = SHARPNESS_HIGH;

	}

	// Translate linear light scaling preference

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

+116 −33
Original line number Diff line number Diff line
@@ -949,6 +949,9 @@ static void dpp401_dscl_set_isharp_filter( 
{

	int level;

	uint32_t filter_data;

	if (filter == NULL)

		return;



	REG_UPDATE(ISHARP_DELTA_CTRL,

		ISHARP_DELTA_LUT_HOST_SELECT, 0);

	for (level = 0; level < NUM_LEVELS; level++)	{
@@ -972,41 +975,121 @@ static void dpp401_dscl_program_isharp(struct dpp *dpp_base, 
		const struct scaler_data *scl_data)

{

	struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

	const struct dscl_prog_data *data;



	if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)

		return;



	PERF_TRACE();

	dpp->scl_data = *scl_data;

	data = &scl_data->dscl_prog_data;



	REG_SET(ISHARP_MODE, 0,	ISHARP_EN, data->isharp_en);



	REG_SET(ISHARP_MODE, 0,	              ISHARP_NOISEDET_EN,    data->isharp_noise_det.enable);

	REG_SET(ISHARP_MODE, 0,               ISHARP_NOISEDET_MODE,  data->isharp_noise_det.mode);

	REG_SET(ISHARP_NOISEDET_THRESHOLD, 0, ISHARP_NOISEDET_UTHRE, data->isharp_noise_det.uthreshold);

	REG_SET(ISHARP_NOISEDET_THRESHOLD, 0, ISHARP_NOISEDET_DTHRE, data->isharp_noise_det.dthreshold);

	REG_SET(ISHARP_MODE, 0,               ISHARP_NOISEDET_MODE,  data->isharp_noise_det.mode);

	REG_SET(ISHARP_NOISEDET_THRESHOLD, 0, ISHARP_NOISEDET_UTHRE, data->isharp_noise_det.uthreshold);

	REG_SET(ISHARP_NOISEDET_THRESHOLD, 0, ISHARP_NOISEDET_DTHRE, data->isharp_noise_det.dthreshold);

	REG_SET(ISHARP_NOISE_GAIN_PWL, 0, ISHARP_NOISEDET_PWL_START_IN, data->isharp_noise_det.pwl_start_in);

	REG_SET(ISHARP_NOISE_GAIN_PWL, 0, ISHARP_NOISEDET_PWL_END_IN, data->isharp_noise_det.pwl_end_in);

	REG_SET(ISHARP_NOISE_GAIN_PWL, 0, ISHARP_NOISEDET_PWL_SLOPE, data->isharp_noise_det.pwl_slope);



	REG_SET(ISHARP_MODE, 0, ISHARP_LBA_MODE, data->isharp_lba.mode);

	// TODO: ISHARP_LBA: IN_SEG, BASE_SEG, SLOPE_SEG

	REG_SET(ISHARP_MODE, 0, ISHARP_FMT_MODE, data->isharp_fmt.mode);

	REG_SET(ISHARP_MODE, 0, ISHARP_FMT_NORM, data->isharp_fmt.norm);



	dpp401_dscl_set_isharp_filter(dpp, data->isharp_delta);



	REG_SET(ISHARP_NLDELTA_SOFT_CLIP, 0, ISHARP_NLDELTA_SCLIP_EN_P,    data->isharp_nldelta_sclip.enable_p);

	REG_SET(ISHARP_NLDELTA_SOFT_CLIP, 0, ISHARP_NLDELTA_SCLIP_PIVOT_P, data->isharp_nldelta_sclip.pivot_p);

	REG_SET(ISHARP_NLDELTA_SOFT_CLIP, 0, ISHARP_NLDELTA_SCLIP_SLOPE_P, data->isharp_nldelta_sclip.slope_p);

	REG_SET(ISHARP_NLDELTA_SOFT_CLIP, 0, ISHARP_NLDELTA_SCLIP_EN_N,    data->isharp_nldelta_sclip.enable_n);

	REG_SET(ISHARP_NLDELTA_SOFT_CLIP, 0, ISHARP_NLDELTA_SCLIP_PIVOT_N, data->isharp_nldelta_sclip.pivot_n);

	REG_SET(ISHARP_NLDELTA_SOFT_CLIP, 0, ISHARP_NLDELTA_SCLIP_SLOPE_N, data->isharp_nldelta_sclip.slope_n);

	/* ISHARP_EN */

	REG_UPDATE(ISHARP_MODE,

		ISHARP_EN, scl_data->dscl_prog_data.isharp_en);

	/* ISHARP_NOISEDET_EN */

	REG_UPDATE(ISHARP_MODE,

		ISHARP_NOISEDET_EN, scl_data->dscl_prog_data.isharp_noise_det.enable);

	/* ISHARP_NOISEDET_MODE */

	REG_UPDATE(ISHARP_MODE,

		ISHARP_NOISEDET_MODE, scl_data->dscl_prog_data.isharp_noise_det.mode);

	/* ISHARP_NOISEDET_UTHRE */

	REG_UPDATE(ISHARP_NOISEDET_THRESHOLD,

		ISHARP_NOISEDET_UTHRE, scl_data->dscl_prog_data.isharp_noise_det.uthreshold);

	/* ISHARP_NOISEDET_DTHRE */

	REG_UPDATE(ISHARP_NOISEDET_THRESHOLD,

		ISHARP_NOISEDET_DTHRE, scl_data->dscl_prog_data.isharp_noise_det.dthreshold);

	REG_UPDATE(ISHARP_MODE,

		ISHARP_NOISEDET_MODE, scl_data->dscl_prog_data.isharp_noise_det.mode);

	/* ISHARP_NOISEDET_UTHRE */

	REG_UPDATE(ISHARP_NOISEDET_THRESHOLD,

		ISHARP_NOISEDET_UTHRE, scl_data->dscl_prog_data.isharp_noise_det.uthreshold);

	/* ISHARP_NOISEDET_DTHRE */

	REG_UPDATE(ISHARP_NOISEDET_THRESHOLD,

		ISHARP_NOISEDET_DTHRE, scl_data->dscl_prog_data.isharp_noise_det.dthreshold);

	/* ISHARP_NOISEDET_PWL_START_IN */

	REG_UPDATE(ISHARP_NOISE_GAIN_PWL,

		ISHARP_NOISEDET_PWL_START_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_start_in);

	/* ISHARP_NOISEDET_PWL_END_IN */

	REG_UPDATE(ISHARP_NOISE_GAIN_PWL,

		ISHARP_NOISEDET_PWL_END_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_end_in);

	/* ISHARP_NOISEDET_PWL_SLOPE */

	REG_UPDATE(ISHARP_NOISE_GAIN_PWL,

		ISHARP_NOISEDET_PWL_SLOPE, scl_data->dscl_prog_data.isharp_noise_det.pwl_slope);

	/* ISHARP_LBA_MODE */

	REG_UPDATE(ISHARP_MODE,

		ISHARP_LBA_MODE, scl_data->dscl_prog_data.isharp_lba.mode);

	/* ISHARP_LBA: IN_SEG, BASE_SEG, SLOPE_SEG */

	REG_UPDATE(ISHARP_LBA_PWL_SEG0,

		ISHARP_LBA_PWL_IN_SEG0, scl_data->dscl_prog_data.isharp_lba.in_seg[0]);

	REG_UPDATE(ISHARP_LBA_PWL_SEG0,

		ISHARP_LBA_PWL_BASE_SEG0, scl_data->dscl_prog_data.isharp_lba.base_seg[0]);

	REG_UPDATE(ISHARP_LBA_PWL_SEG0,

		ISHARP_LBA_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.isharp_lba.slope_seg[0]);

	REG_UPDATE(ISHARP_LBA_PWL_SEG1,

		ISHARP_LBA_PWL_IN_SEG1, scl_data->dscl_prog_data.isharp_lba.in_seg[1]);

	REG_UPDATE(ISHARP_LBA_PWL_SEG1,

		ISHARP_LBA_PWL_BASE_SEG1, scl_data->dscl_prog_data.isharp_lba.base_seg[1]);

	REG_UPDATE(ISHARP_LBA_PWL_SEG1,

		ISHARP_LBA_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.isharp_lba.slope_seg[1]);

	REG_UPDATE(ISHARP_LBA_PWL_SEG2,

		ISHARP_LBA_PWL_IN_SEG2, scl_data->dscl_prog_data.isharp_lba.in_seg[2]);

	REG_UPDATE(ISHARP_LBA_PWL_SEG2,

		ISHARP_LBA_PWL_BASE_SEG2, scl_data->dscl_prog_data.isharp_lba.base_seg[2]);

	REG_UPDATE(ISHARP_LBA_PWL_SEG2,

		ISHARP_LBA_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.isharp_lba.slope_seg[2]);

	REG_UPDATE(ISHARP_LBA_PWL_SEG3,

		ISHARP_LBA_PWL_IN_SEG3, scl_data->dscl_prog_data.isharp_lba.in_seg[3]);

	REG_UPDATE(ISHARP_LBA_PWL_SEG3,

		ISHARP_LBA_PWL_BASE_SEG3, scl_data->dscl_prog_data.isharp_lba.base_seg[3]);

	REG_UPDATE(ISHARP_LBA_PWL_SEG3,

		ISHARP_LBA_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.isharp_lba.slope_seg[3]);

	REG_UPDATE(ISHARP_LBA_PWL_SEG4,

		ISHARP_LBA_PWL_IN_SEG4, scl_data->dscl_prog_data.isharp_lba.in_seg[4]);

	REG_UPDATE(ISHARP_LBA_PWL_SEG4,

		ISHARP_LBA_PWL_BASE_SEG4, scl_data->dscl_prog_data.isharp_lba.base_seg[4]);

	REG_UPDATE(ISHARP_LBA_PWL_SEG4,

		ISHARP_LBA_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.isharp_lba.slope_seg[4]);

	REG_UPDATE(ISHARP_LBA_PWL_SEG5,

		ISHARP_LBA_PWL_IN_SEG5, scl_data->dscl_prog_data.isharp_lba.in_seg[5]);

	REG_UPDATE(ISHARP_LBA_PWL_SEG5,

		ISHARP_LBA_PWL_BASE_SEG5, scl_data->dscl_prog_data.isharp_lba.base_seg[5]);



	/* ISHARP_FMT_MODE */

	REG_UPDATE(ISHARP_MODE,

		ISHARP_FMT_MODE, scl_data->dscl_prog_data.isharp_fmt.mode);

	/* ISHARP_FMT_NORM */

	REG_UPDATE(ISHARP_MODE,

		ISHARP_FMT_NORM, scl_data->dscl_prog_data.isharp_fmt.norm);

	/* ISHARP_DELTA_LUT */

	dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta);

	/* ISHARP_NLDELTA_SCLIP_EN_P */

	REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP,

		ISHARP_NLDELTA_SCLIP_EN_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_p);

	/* ISHARP_NLDELTA_SCLIP_PIVOT_P */

	REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP,

		ISHARP_NLDELTA_SCLIP_PIVOT_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_p);

	/* ISHARP_NLDELTA_SCLIP_SLOPE_P */

	REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP,

		ISHARP_NLDELTA_SCLIP_SLOPE_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_p);

	/* ISHARP_NLDELTA_SCLIP_EN_N */

	REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP,

		ISHARP_NLDELTA_SCLIP_EN_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_n);

	/* ISHARP_NLDELTA_SCLIP_PIVOT_N */

	REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP,

		ISHARP_NLDELTA_SCLIP_PIVOT_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_n);

	/* ISHARP_NLDELTA_SCLIP_SLOPE_N */

	REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP,

		ISHARP_NLDELTA_SCLIP_SLOPE_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_n);



	/* Blur and Scale Coefficients - SCL_COEF_RAM_TAP_SELECT */

	if (scl_data->dscl_prog_data.isharp_en) {

		if (scl_data->dscl_prog_data.filter_blur_scale_v) {

			dpp401_dscl_set_scaler_filter(

				dpp, scl_data->taps.v_taps,

				SCL_COEF_VERTICAL_BLUR_SCALE,

				scl_data->dscl_prog_data.filter_blur_scale_v);

		}

		if (scl_data->dscl_prog_data.filter_blur_scale_h) {

			dpp401_dscl_set_scaler_filter(

				dpp, scl_data->taps.h_taps,

				SCL_COEF_HORIZONTAL_BLUR_SCALE,

				scl_data->dscl_prog_data.filter_blur_scale_h);

		}

	}

	PERF_TRACE();

} // dpp401_dscl_program_isharp

/**

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

+13 −0
Original line number Diff line number Diff line
@@ -387,6 +387,19 @@ bool dcn401_validate_bandwidth(struct dc *dc, 
	SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG5, DSCL, id),                             \

	SRI_ARR(DSCL_SC_MATRIX_C0C1, DSCL, id),                                  \

	SRI_ARR(DSCL_SC_MATRIX_C2C3, DSCL, id),                                  \

	SRI_ARR(ISHARP_MODE, DSCL, id),                                          \

	SRI_ARR(ISHARP_NOISEDET_THRESHOLD, DSCL, id),                            \

	SRI_ARR(ISHARP_NOISE_GAIN_PWL, DSCL, id),                                \

	SRI_ARR(ISHARP_LBA_PWL_SEG0, DSCL, id),                                  \

	SRI_ARR(ISHARP_LBA_PWL_SEG1, DSCL, id),                                  \

	SRI_ARR(ISHARP_LBA_PWL_SEG2, DSCL, id),                                  \

	SRI_ARR(ISHARP_LBA_PWL_SEG3, DSCL, id),                                  \

	SRI_ARR(ISHARP_LBA_PWL_SEG4, DSCL, id),                                  \

	SRI_ARR(ISHARP_LBA_PWL_SEG5, DSCL, id),                                  \

	SRI_ARR(ISHARP_DELTA_CTRL, DSCL, id),                                    \

	SRI_ARR(ISHARP_DELTA_DATA, DSCL, id),                                    \

	SRI_ARR(ISHARP_DELTA_INDEX, DSCL, id),                                   \

	SRI_ARR(ISHARP_NLDELTA_SOFT_CLIP, DSCL, id),                             \

	SRI_ARR(SCL_VERT_FILTER_INIT_BOT, DSCL, id),                             \

	SRI_ARR(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id)

drivers/gpu/drm/amd/display/dc/spl/dc_spl.c

+65 −16
Original line number Diff line number Diff line
@@ -913,6 +913,25 @@ static void spl_set_filters_data(struct dscl_prog_data *dscl_prog_data, 
	dscl_prog_data->filter_v_c = spl_dscl_get_filter_coeffs_64p(

				data->taps.v_taps_c, data->ratios.vert_c);

}



static const uint16_t *spl_dscl_get_blur_scale_coeffs_64p(int taps)

{

	if ((taps == 3) || (taps == 4) || (taps == 6))

		return spl_get_filter_isharp_bs_4tap_64p();

	else {

		/* should never happen, bug */

		return NULL;

	}

}

static void spl_set_blur_scale_data(struct dscl_prog_data *dscl_prog_data,

		const struct spl_scaler_data *data)

{

	dscl_prog_data->filter_blur_scale_h = spl_dscl_get_blur_scale_coeffs_64p(

				data->taps.h_taps);

	dscl_prog_data->filter_blur_scale_v = spl_dscl_get_blur_scale_coeffs_64p(

				data->taps.v_taps);

}



/* Populate dscl prog data structure from scaler data calculated by SPL */

static void spl_set_dscl_prog_data(struct spl_in *spl_in, struct spl_out *spl_out)

{
@@ -1226,10 +1245,18 @@ static void spl_set_isharp_noise_det_mode(struct dscl_prog_data *dscl_prog_data) 
	else if (dscl_prog_data->taps.h_taps == 3)

		dscl_prog_data->isharp_noise_det.mode = 0;	// ISHARP_NOISEDET_MODE

};

/* Set EASF data */

/* Set Sharpener data */

static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data,

		struct adaptive_sharpness adp_sharpness)

		struct adaptive_sharpness adp_sharpness, bool enable_isharp,

		enum linear_light_scaling lls_pref, enum spl_pixel_format format,

		const struct spl_scaler_data *data)

{

	/* Turn off sharpener if not required */

	if (!enable_isharp) {

		dscl_prog_data->isharp_en = 0;

		return;

	}



	dscl_prog_data->isharp_en = 1;	// ISHARP_EN

	dscl_prog_data->isharp_noise_det.enable = 1;	// ISHARP_NOISEDET_EN

	// Set ISHARP_NOISEDET_MODE if htaps = 6-tap
@@ -1243,7 +1270,11 @@ static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data, 
	dscl_prog_data->isharp_noise_det.pwl_end_in = 13;	// ISHARP_NOISEDET_PWL_END_IN

	dscl_prog_data->isharp_noise_det.pwl_slope = 1623;	// ISHARP_NOISEDET_PWL_SLOPE



	dscl_prog_data->isharp_fmt.mode = 1;	//	ISHARP_FMT_MODE

	if ((lls_pref == LLS_PREF_NO) && !spl_is_yuv420(format)) /* ISHARP_FMT_MODE */

		dscl_prog_data->isharp_fmt.mode = 1;

	else

		dscl_prog_data->isharp_fmt.mode = 0;



	dscl_prog_data->isharp_fmt.norm = 0x3C00;	// ISHARP_FMT_NORM

	dscl_prog_data->isharp_lba.mode = 0;	// ISHARP_LBA_MODE

	// ISHARP_LBA_PWL_SEG0: ISHARP Local Brightness Adjustment PWL Segment 0
@@ -1284,17 +1315,28 @@ static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data, 
	}



	// Program the nldelta soft clip values

	dscl_prog_data->isharp_nldelta_sclip.enable_p = 1;	//	ISHARP_NLDELTA_SCLIP_EN_P

	dscl_prog_data->isharp_nldelta_sclip.pivot_p = 70;	//	ISHARP_NLDELTA_SCLIP_PIVOT_P

	dscl_prog_data->isharp_nldelta_sclip.slope_p = 24;	//	ISHARP_NLDELTA_SCLIP_SLOPE_P

	dscl_prog_data->isharp_nldelta_sclip.enable_n = 1;	//	ISHARP_NLDELTA_SCLIP_EN_N

	dscl_prog_data->isharp_nldelta_sclip.pivot_n = 70;	//	ISHARP_NLDELTA_SCLIP_PIVOT_N

	dscl_prog_data->isharp_nldelta_sclip.slope_n = 24;	//	ISHARP_NLDELTA_SCLIP_SLOPE_N

	if (lls_pref == LLS_PREF_YES) {

		dscl_prog_data->isharp_nldelta_sclip.enable_p = 0;	/* ISHARP_NLDELTA_SCLIP_EN_P */

		dscl_prog_data->isharp_nldelta_sclip.pivot_p = 0;	/* ISHARP_NLDELTA_SCLIP_PIVOT_P */

		dscl_prog_data->isharp_nldelta_sclip.slope_p = 0;	/* ISHARP_NLDELTA_SCLIP_SLOPE_P */

		dscl_prog_data->isharp_nldelta_sclip.enable_n = 1;	/* ISHARP_NLDELTA_SCLIP_EN_N */

		dscl_prog_data->isharp_nldelta_sclip.pivot_n = 71;	/* ISHARP_NLDELTA_SCLIP_PIVOT_N */

		dscl_prog_data->isharp_nldelta_sclip.slope_n = 16;	/* ISHARP_NLDELTA_SCLIP_SLOPE_N */

	} else {

		dscl_prog_data->isharp_nldelta_sclip.enable_p = 1;	/* ISHARP_NLDELTA_SCLIP_EN_P */

		dscl_prog_data->isharp_nldelta_sclip.pivot_p = 70;	/* ISHARP_NLDELTA_SCLIP_PIVOT_P */

		dscl_prog_data->isharp_nldelta_sclip.slope_p = 24;	/* ISHARP_NLDELTA_SCLIP_SLOPE_P */

		dscl_prog_data->isharp_nldelta_sclip.enable_n = 1;	/* ISHARP_NLDELTA_SCLIP_EN_N */

		dscl_prog_data->isharp_nldelta_sclip.pivot_n = 70;	/* ISHARP_NLDELTA_SCLIP_PIVOT_N */

		dscl_prog_data->isharp_nldelta_sclip.slope_n = 24;	/* ISHARP_NLDELTA_SCLIP_SLOPE_N */

	}



	// Set the values as per lookup table

	spl_set_blur_scale_data(dscl_prog_data, data);

}

static bool spl_get_isharp_en(struct adaptive_sharpness adp_sharpness,

		int vscale_ratio, int hscale_ratio, struct spl_taps taps)

		int vscale_ratio, int hscale_ratio, struct spl_taps taps,

		enum spl_pixel_format format)

{

	bool enable_isharp = false;
@@ -1307,6 +1349,10 @@ static bool spl_get_isharp_en(struct adaptive_sharpness adp_sharpness, 
	}

	// Scaling is up to 1:1 (no scaling) or upscaling



	/* Only apply sharpness to NV12 and not P010 */

	if (format != SPL_PIXEL_FORMAT_420BPP8)

		return enable_isharp;



	// LB support horizontal taps 4,6 or vertical taps 3, 4, 6

	if (taps.h_taps == 4 || taps.h_taps == 6 ||

		taps.v_taps == 3 || taps.v_taps == 4 || taps.v_taps == 6) {
@@ -1342,13 +1388,14 @@ static bool spl_choose_lls_policy(enum spl_pixel_format format, 
	return false;

}



/* Caclulate scaler parameters */

/* Calculate scaler parameters */

bool spl_calculate_scaler_params(struct spl_in *spl_in, struct spl_out *spl_out)

{

	bool res = false;

	bool enable_easf_v = false;

	bool enable_easf_h = false;

	bool lls_enable_easf = true;

	const struct spl_scaler_data *data = &spl_out->scl_data;

	// All SPL calls

	/* recout calculation */

	/* depends on h_active */
@@ -1400,10 +1447,12 @@ bool spl_calculate_scaler_params(struct spl_in *spl_in, struct spl_out *spl_out) 
	}

	// Set EASF

	spl_set_easf_data(spl_out->dscl_prog_data, enable_easf_v, enable_easf_h, spl_in->lls_pref,

		spl_in->basic_in.format);	// Set iSHARP

		spl_in->basic_in.format);

	// Set iSHARP

	bool enable_isharp = spl_get_isharp_en(spl_in->adaptive_sharpness, vratio, hratio,

								spl_out->scl_data.taps);

	if (enable_isharp)

		spl_set_isharp_data(spl_out->dscl_prog_data, spl_in->adaptive_sharpness);

		spl_out->scl_data.taps, spl_in->basic_in.format);

	spl_set_isharp_data(spl_out->dscl_prog_data, spl_in->adaptive_sharpness, enable_isharp,

		spl_in->lls_pref, spl_in->basic_in.format, data);



	return res;

}