Commit 29e087f3 authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm/registers: Make TPL1_BICUBIC_WEIGHTS_TABLE an array 



Synced from mesa commit 77c42c1a5752 ("freedreno/registers: Make
TPL1_BICUBIC_WEIGHTS_TABLE an array").

Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673552/
parent 90528176

drivers/gpu/drm/msm/adreno/a6xx_catalog.c

+5 −5
Original line number Diff line number Diff line
@@ -1355,11 +1355,11 @@ DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist); 


/* Applicable for X185, A750 */

static const u32 a750_ifpc_reglist_regs[] = {

	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0,

	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,

	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,

	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,

	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,

	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(0),

	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(1),

	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2),

	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3),

	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4),

	REG_A6XX_TPL1_NC_MODE_CNTL,

	REG_A6XX_SP_NC_MODE_CNTL,

	REG_A6XX_CP_DBG_ECO_CNTL,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+5 −5
Original line number Diff line number Diff line
@@ -1337,14 +1337,14 @@ static int hw_init(struct msm_gpu *gpu) 


	/* Set weights for bicubic filtering */

	if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) {

		gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);

		gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,

		gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), 0);

		gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(1),

			0x3fe05ff4);

		gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,

		gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2),

			0x3fa0ebee);

		gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,

		gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3),

			0x3f5193ed);

		gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,

		gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4),

			0x3f0243f0);

	}

drivers/gpu/drm/msm/registers/adreno/a6xx.xml

+7 −11
Original line number Diff line number Diff line
@@ -3296,17 +3296,13 @@ by a particular renderpass/blit. 
	</reg32>

	<reg32 offset="0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint" variants="A6XX" usage="cmd"/> <!-- always 0x0 or 0x44 ? -->



	<reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A6XX"/>

	<reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A6XX"/>

	<reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A6XX"/>

	<reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A6XX"/>

	<reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A6XX"/>



	<reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A7XX" usage="cmd"/>

	<reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A7XX" usage="cmd"/>

	<reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A7XX" usage="cmd"/>

	<reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A7XX" usage="cmd"/>

	<reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A7XX" usage="cmd"/>

	<array offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE" stride="1" length="5" variants="A6XX">

		<reg32 offset="0" name="REG" low="0" high="29"/>

	</array>



	<array offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE" stride="1" length="5" variants="A7XX">

		<reg32 offset="0" name="REG" low="0" high="29" usage="cmd"/>

	</array>



	<array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="12" variants="A6XX"/>

	<array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="18" variants="A7XX"/>