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dt-bindings: clock: fsl-sai: Document i.MX8M support
The i.MX8M/Mini/Nano/Plus variant of the SAI IP has control registers shifted by +8 bytes and requires additional bus clock. Document support for the i.MX8M variant of the IP with this register shift and additional clock. Update the description slightly. Acked-by:Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
Marek Vasut <marex@nabladev.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>