Commit 29f560a5 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: add SMUIO 15.0.0 headers 



Add headers for SMUIO 15.0.0.

v2: squash in updates (Alex)

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fc136601

drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_15_0_0_offset.h

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/*

 * Copyright (C) 2025  Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included

 * in all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN

 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 */

#ifndef _smuio_15_0_0_OFFSET_HEADER

#define _smuio_15_0_0_OFFSET_HEADER







// addressBlock: smuio_smuio_misc_SmuSmuioDec

// base address: 0x5a000

#define regSMUIO_MCM_CONFIG                                                                             0x0023

#define regSMUIO_MCM_CONFIG_BASE_IDX                                                                    0

#define regIP_DISCOVERY_VERSION                                                                         0x0000

#define regIP_DISCOVERY_VERSION_BASE_IDX                                                                1

#define regSCRATCH_REGISTER0                                                                            0x01c6

#define regSCRATCH_REGISTER0_BASE_IDX                                                                   1

#define regSCRATCH_REGISTER1                                                                            0x01c7

#define regSCRATCH_REGISTER1_BASE_IDX                                                                   1

#define regSCRATCH_REGISTER2                                                                            0x01c8

#define regSCRATCH_REGISTER2_BASE_IDX                                                                   1

#define regSCRATCH_REGISTER3                                                                            0x01c9

#define regSCRATCH_REGISTER3_BASE_IDX                                                                   1

#define regSCRATCH_REGISTER4                                                                            0x01ca

#define regSCRATCH_REGISTER4_BASE_IDX                                                                   1

#define regSCRATCH_REGISTER5                                                                            0x01cb

#define regSCRATCH_REGISTER5_BASE_IDX                                                                   1

#define regSCRATCH_REGISTER6                                                                            0x01cc

#define regSCRATCH_REGISTER6_BASE_IDX                                                                   1

#define regSCRATCH_REGISTER7                                                                            0x01cd

#define regSCRATCH_REGISTER7_BASE_IDX                                                                   1

#define regIO_SMUIO_PINSTRAP                                                                            0x01ce

#define regIO_SMUIO_PINSTRAP_BASE_IDX                                                                   1





// addressBlock: smuio_smuio_reset_SmuSmuioDec

// base address: 0x5a300

#define regSMUIO_GFX_MISC_CNTL                                                                          0x00c5

#define regSMUIO_GFX_MISC_CNTL_BASE_IDX                                                                 0





// addressBlock: smuio_smuio_tsc_SmuSmuioDec

// base address: 0x5a8a0

#define regPWROK_REFCLK_GAP_CYCLES                                                                      0x0028

#define regPWROK_REFCLK_GAP_CYCLES_BASE_IDX                                                             1

#define regGOLDEN_TSC_INCREMENT_UPPER                                                                   0x002b

#define regGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX                                                          1

#define regGOLDEN_TSC_INCREMENT_LOWER                                                                   0x002c

#define regGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX                                                          1

#define regGOLDEN_TSC_COUNT_UPPER                                                                       0x0030

#define regGOLDEN_TSC_COUNT_UPPER_BASE_IDX                                                              1

#define regGOLDEN_TSC_COUNT_LOWER                                                                       0x0031

#define regGOLDEN_TSC_COUNT_LOWER_BASE_IDX                                                              1

#define regSOC_GOLDEN_TSC_SHADOW_UPPER                                                                  0x0032

#define regSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX                                                         1

#define regSOC_GOLDEN_TSC_SHADOW_LOWER                                                                  0x0033

#define regSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX                                                         1

#define regSOC_GAP_PWROK                                                                                0x0034

#define regSOC_GAP_PWROK_BASE_IDX                                                                       1





// addressBlock: smuio_smuio_swtimer_SmuSmuioDec

// base address: 0x5aca8

#define regPWR_VIRT_RESET_REQ                                                                           0x012a

#define regPWR_VIRT_RESET_REQ_BASE_IDX                                                                  1

#define regPWR_DISP_TIMER_CONTROL                                                                       0x012b

#define regPWR_DISP_TIMER_CONTROL_BASE_IDX                                                              1

#define regPWR_DISP_TIMER_DEBUG                                                                         0x012c

#define regPWR_DISP_TIMER_DEBUG_BASE_IDX                                                                1

#define regPWR_DISP_TIMER_ELAPSED_CONTROL                                                               0x012d

#define regPWR_DISP_TIMER_ELAPSED_CONTROL_BASE_IDX                                                      1

#define regPWR_DISP_TIMER2_CONTROL                                                                      0x012e

#define regPWR_DISP_TIMER2_CONTROL_BASE_IDX                                                             1

#define regPWR_DISP_TIMER2_DEBUG                                                                        0x012f

#define regPWR_DISP_TIMER2_DEBUG_BASE_IDX                                                               1

#define regPWR_DISP_TIMER2_ELAPSED_CONTROL                                                              0x0130

#define regPWR_DISP_TIMER2_ELAPSED_CONTROL_BASE_IDX                                                     1

#define regPWR_DISP_TIMER_GLOBAL_CONTROL                                                                0x0131

#define regPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX                                                       1

#define regPWR_IH_CONTROL                                                                               0x0132

#define regPWR_IH_CONTROL_BASE_IDX                                                                      1





#endif

drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_15_0_0_sh_mask.h

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/*

 * Copyright (C) 2025  Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included

 * in all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN

 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 */

#ifndef _smuio_15_0_0_SH_MASK_HEADER

#define _smuio_15_0_0_SH_MASK_HEADER





// addressBlock: smuio_smuio_misc_SmuSmuioDec

//SMUIO_MCM_CONFIG

#define SMUIO_MCM_CONFIG__DIE_ID__SHIFT                                                                       0x0

#define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT                                                                     0x2

#define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT                                                                    0x8

#define SMUIO_MCM_CONFIG__CONSOLE_K__SHIFT                                                                    0x10

#define SMUIO_MCM_CONFIG__CONSOLE_A__SHIFT                                                                    0x11

#define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT                                                                  0x12

#define SMUIO_MCM_CONFIG__DIE_ID_MASK                                                                         0x00000003L

#define SMUIO_MCM_CONFIG__PKG_TYPE_MASK                                                                       0x0000003CL

#define SMUIO_MCM_CONFIG__SOCKET_ID_MASK                                                                      0x00000100L

#define SMUIO_MCM_CONFIG__CONSOLE_K_MASK                                                                      0x00010000L

#define SMUIO_MCM_CONFIG__CONSOLE_A_MASK                                                                      0x00020000L

#define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK                                                                    0x00040000L

//IP_DISCOVERY_VERSION

#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT                                                     0x0

#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK                                                       0xFFFFFFFFL

//SCRATCH_REGISTER0

#define SCRATCH_REGISTER0__ScratchPad0__SHIFT                                                                 0x0

#define SCRATCH_REGISTER0__ScratchPad0_MASK                                                                   0xFFFFFFFFL

//SCRATCH_REGISTER1

#define SCRATCH_REGISTER1__ScratchPad1__SHIFT                                                                 0x0

#define SCRATCH_REGISTER1__ScratchPad1_MASK                                                                   0xFFFFFFFFL

//SCRATCH_REGISTER2

#define SCRATCH_REGISTER2__ScratchPad2__SHIFT                                                                 0x0

#define SCRATCH_REGISTER2__ScratchPad2_MASK                                                                   0xFFFFFFFFL

//SCRATCH_REGISTER3

#define SCRATCH_REGISTER3__ScratchPad3__SHIFT                                                                 0x0

#define SCRATCH_REGISTER3__ScratchPad3_MASK                                                                   0xFFFFFFFFL

//SCRATCH_REGISTER4

#define SCRATCH_REGISTER4__ScratchPad4__SHIFT                                                                 0x0

#define SCRATCH_REGISTER4__ScratchPad4_MASK                                                                   0xFFFFFFFFL

//SCRATCH_REGISTER5

#define SCRATCH_REGISTER5__ScratchPad5__SHIFT                                                                 0x0

#define SCRATCH_REGISTER5__ScratchPad5_MASK                                                                   0xFFFFFFFFL

//SCRATCH_REGISTER6

#define SCRATCH_REGISTER6__ScratchPad6__SHIFT                                                                 0x0

#define SCRATCH_REGISTER6__ScratchPad6_MASK                                                                   0xFFFFFFFFL

//SCRATCH_REGISTER7

#define SCRATCH_REGISTER7__ScratchPad7__SHIFT                                                                 0x0

#define SCRATCH_REGISTER7__ScratchPad7_MASK                                                                   0xFFFFFFFFL

//IO_SMUIO_PINSTRAP

#define IO_SMUIO_PINSTRAP__AUD_PORT_CONN__SHIFT                                                               0x0

#define IO_SMUIO_PINSTRAP__AUD__SHIFT                                                                         0x3

#define IO_SMUIO_PINSTRAP__AUD_PORT_CONN_MASK                                                                 0x00000007L

#define IO_SMUIO_PINSTRAP__AUD_MASK                                                                           0x00000018L





// addressBlock: smuio_smuio_reset_SmuSmuioDec

//SMUIO_GFX_MISC_CNTL

#define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT                                                    0x0

#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT                                                         0x1

#define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK                                                      0x00000001L

#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK                                                           0x00000006L





// addressBlock: smuio_smuio_tsc_SmuSmuioDec

//PWROK_REFCLK_GAP_CYCLES

#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT                                      0x0

#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT                                     0x8

#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK                                        0x000000FFL

#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK                                       0x0000FF00L

//GOLDEN_TSC_INCREMENT_UPPER

#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT                                            0x0

#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK                                              0x00FFFFFFL

//GOLDEN_TSC_INCREMENT_LOWER

#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT                                            0x0

#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK                                              0xFFFFFFFFL

//GOLDEN_TSC_COUNT_UPPER

#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT                                                    0x0

#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK                                                      0x00FFFFFFL

//GOLDEN_TSC_COUNT_LOWER

#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT                                                    0x0

#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK                                                      0xFFFFFFFFL

//SOC_GOLDEN_TSC_SHADOW_UPPER

#define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper__SHIFT                                           0x0

#define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper_MASK                                             0x00FFFFFFL

//SOC_GOLDEN_TSC_SHADOW_LOWER

#define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower__SHIFT                                           0x0

#define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower_MASK                                             0xFFFFFFFFL

//SOC_GAP_PWROK

#define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT                                                                   0x0

#define SOC_GAP_PWROK__soc_gap_pwrok_MASK                                                                     0x00000001L





// addressBlock: smuio_smuio_swtimer_SmuSmuioDec

//PWR_VIRT_RESET_REQ

#define PWR_VIRT_RESET_REQ__VF_FLR__SHIFT                                                                     0x0

#define PWR_VIRT_RESET_REQ__PF_FLR__SHIFT                                                                     0x1f

#define PWR_VIRT_RESET_REQ__VF_FLR_MASK                                                                       0x7FFFFFFFL

#define PWR_VIRT_RESET_REQ__PF_FLR_MASK                                                                       0x80000000L

//PWR_DISP_TIMER_CONTROL

#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT                                                   0x0

#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT                                                  0x19

#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT                                                 0x1a

#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT                                                    0x1b

#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT                                                 0x1c

#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT                                                    0x1d

#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT                                                    0x1e

#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK                                                     0x01FFFFFFL

#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK                                                    0x02000000L

#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK                                                   0x04000000L

#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK                                                      0x08000000L

#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK                                                   0x10000000L

#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK                                                      0x20000000L

#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK                                                      0x40000000L

//PWR_DISP_TIMER_DEBUG

#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT                                                   0x0

#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT__SHIFT                                                      0x1

#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT__SHIFT                                                           0x2

#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL__SHIFT                                                       0x7

#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING_MASK                                                     0x00000001L

#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT_MASK                                                        0x00000002L

#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_MASK                                                             0x00000004L

#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL_MASK                                                         0xFFFFFF80L

//PWR_DISP_TIMER_ELAPSED_CONTROL

#define PWR_DISP_TIMER_ELAPSED_CONTROL__DISP_TIMER_ELAPSED_TIME_COUNT__SHIFT                                  0x0

#define PWR_DISP_TIMER_ELAPSED_CONTROL__DISP_TIMER_COMP_ENABLE__SHIFT                                         0x19

#define PWR_DISP_TIMER_ELAPSED_CONTROL__DISP_TIMER_ELAPSED_TIME_COUNT_MASK                                    0x01FFFFFFL

#define PWR_DISP_TIMER_ELAPSED_CONTROL__DISP_TIMER_COMP_ENABLE_MASK                                           0x02000000L

//PWR_DISP_TIMER2_CONTROL

#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT                                                  0x0

#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT                                                 0x19

#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT                                                0x1a

#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT                                                   0x1b

#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT                                                0x1c

#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT                                                   0x1d

#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT                                                   0x1e

#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK                                                    0x01FFFFFFL

#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK                                                   0x02000000L

#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK                                                  0x04000000L

#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK                                                     0x08000000L

#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK                                                  0x10000000L

#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK                                                     0x20000000L

#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK                                                     0x40000000L

//PWR_DISP_TIMER2_DEBUG

#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT                                                  0x0

#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT__SHIFT                                                     0x1

#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT__SHIFT                                                          0x2

#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL__SHIFT                                                      0x7

#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING_MASK                                                    0x00000001L

#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT_MASK                                                       0x00000002L

#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_MASK                                                            0x00000004L

#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL_MASK                                                        0xFFFFFF80L

//PWR_DISP_TIMER2_ELAPSED_CONTROL

#define PWR_DISP_TIMER2_ELAPSED_CONTROL__DISP_TIMER_ELAPSED_TIME_COUNT__SHIFT                                 0x0

#define PWR_DISP_TIMER2_ELAPSED_CONTROL__DISP_TIMER_COMP_ENABLE__SHIFT                                        0x19

#define PWR_DISP_TIMER2_ELAPSED_CONTROL__DISP_TIMER_ELAPSED_TIME_COUNT_MASK                                   0x01FFFFFFL

#define PWR_DISP_TIMER2_ELAPSED_CONTROL__DISP_TIMER_COMP_ENABLE_MASK                                          0x02000000L

//PWR_DISP_TIMER_GLOBAL_CONTROL

#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT                                          0x0

#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT                                             0xa

#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK                                            0x000003FFL

#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK                                               0x00000400L

//PWR_IH_CONTROL

#define PWR_IH_CONTROL__MAX_CREDIT__SHIFT                                                                     0x0

#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT                                                        0x5

#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT                                                       0x6

#define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN__SHIFT                                                             0x1f

#define PWR_IH_CONTROL__MAX_CREDIT_MASK                                                                       0x0000001FL

#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK                                                          0x00000020L

#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK                                                         0x00000040L

#define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN_MASK                                                               0x80000000L





#endif