Commit 2a1944bf authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-6.14-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Palmer Dabbelt:

 - A fix for cacheinfo DT probing to avoid reading non-boolean
   properties as booleans.

 - A fix for cpufeature to use bitmap_equal() instead of memcmp(), so
   unused bits are ignored.

 - Fixes for cmpxchg and futex cmpxchg that properly encode the sign
   extension requirements on inline asm, which results in spurious
   successes. This manifests in at least inode_set_ctime_current, but is
   likely just a disaster waiting to happen.

 - A fix for the rseq selftests, which was using an invalid constraint.

 - A pair of fixes for signal frame size handling:

     - We were reserving space for an extra empty extension context
       header on systems with extended signal context, thus resulting in
       unnecessarily large allocations.

     - We weren't properly checking for available extensions before
       calculating the signal stack size, which resulted in undersized
       stack allocations on some systems (at least those with T-Head
       custom vectors).

Also, we've added Alex as a reviewer.  He's been helping out a ton
lately, thanks!

* tag 'riscv-for-linus-6.14-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  MAINTAINERS: Add myself as a riscv reviewer
  riscv: signal: fix signal_minsigstksz
  riscv: signal: fix signal frame size
  rseq/selftests: Fix riscv rseq_offset_deref_addv inline asm
  riscv/futex: sign extend compare value in atomic cmpxchg
  riscv/atomic: Do proper sign extension also for unsigned in arch_cmpxchg
  riscv: cpufeature: use bitmap_equal() instead of memcmp()
  riscv: cacheinfo: Use of_property_present() for non-boolean properties
parents 2c24478e 245aece3
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+1 −0
Original line number Diff line number Diff line
@@ -20328,6 +20328,7 @@ RISC-V ARCHITECTURE
M:	Paul Walmsley <paul.walmsley@sifive.com>
M:	Palmer Dabbelt <palmer@dabbelt.com>
M:	Albert Ou <aou@eecs.berkeley.edu>
R:	Alexandre Ghiti <alex@ghiti.fr>
L:	linux-riscv@lists.infradead.org
S:	Supported
Q:	https://patchwork.kernel.org/project/linux-riscv/list/
+1 −1
Original line number Diff line number Diff line
@@ -231,7 +231,7 @@
		__arch_cmpxchg(".w", ".w" sc_sfx, ".w" cas_sfx,		\
			       sc_prepend, sc_append,			\
			       cas_prepend, cas_append,			\
			       __ret, __ptr, (long), __old, __new);	\
			       __ret, __ptr, (long)(int)(long), __old, __new);	\
		break;							\
	case 8:								\
		__arch_cmpxchg(".d", ".d" sc_sfx, ".d" cas_sfx,		\
+1 −1
Original line number Diff line number Diff line
@@ -93,7 +93,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
		_ASM_EXTABLE_UACCESS_ERR(1b, 3b, %[r])	\
		_ASM_EXTABLE_UACCESS_ERR(2b, 3b, %[r])	\
	: [r] "+r" (ret), [v] "=&r" (val), [u] "+m" (*uaddr), [t] "=&r" (tmp)
	: [ov] "Jr" (oldval), [nv] "Jr" (newval)
	: [ov] "Jr" ((long)(int)oldval), [nv] "Jr" (newval)
	: "memory");
	__disable_user_access();

+6 −6
Original line number Diff line number Diff line
@@ -108,11 +108,11 @@ int populate_cache_leaves(unsigned int cpu)
	if (!np)
		return -ENOENT;

	if (of_property_read_bool(np, "cache-size"))
	if (of_property_present(np, "cache-size"))
		ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
	if (of_property_read_bool(np, "i-cache-size"))
	if (of_property_present(np, "i-cache-size"))
		ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
	if (of_property_read_bool(np, "d-cache-size"))
	if (of_property_present(np, "d-cache-size"))
		ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);

	prev = np;
@@ -125,11 +125,11 @@ int populate_cache_leaves(unsigned int cpu)
			break;
		if (level <= levels)
			break;
		if (of_property_read_bool(np, "cache-size"))
		if (of_property_present(np, "cache-size"))
			ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
		if (of_property_read_bool(np, "i-cache-size"))
		if (of_property_present(np, "i-cache-size"))
			ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
		if (of_property_read_bool(np, "d-cache-size"))
		if (of_property_present(np, "d-cache-size"))
			ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
		levels = level;
	}
+1 −1
Original line number Diff line number Diff line
@@ -479,7 +479,7 @@ static void __init riscv_resolve_isa(unsigned long *source_isa,
			if (bit < RISCV_ISA_EXT_BASE)
				*this_hwcap |= isa2hwcap[bit];
		}
	} while (loop && memcmp(prev_resolved_isa, resolved_isa, sizeof(prev_resolved_isa)));
	} while (loop && !bitmap_equal(prev_resolved_isa, resolved_isa, RISCV_ISA_EXT_MAX));
}

static void __init match_isa_ext(const char *name, const char *name_end, unsigned long *bitmap)
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