Commit 2a77d015 authored by Ben Skeggs's avatar Ben Skeggs Committed by Dave Airlie
Browse files

drm/nouveau/fifo/r535: initial support 



- Adds support for allocating CHANNEL_GPFIFO classes from RM.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230918202149.4343-39-skeggsb@gmail.com
parent 9e994444

drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h

+13 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
#include <core/engine.h>

#include <core/object.h>

#include <core/event.h>

#include <subdev/gsp.h>

struct nvkm_fault_data;



#define NVKM_FIFO_ENGN_NR 16
@@ -35,6 +36,14 @@ struct nvkm_chan { 
	atomic_t blocked;

	atomic_t errored;



	struct {

		struct nvkm_gsp_object object;

		struct {

			dma_addr_t addr;

			void *ptr;

		} mthdbuf;

	} rm;



	struct list_head cctxs;

	struct list_head head;

};
@@ -71,6 +80,10 @@ struct nvkm_fifo { 
		struct list_head list;

	} userd;



	struct {

		u32 mthdbuf_size;

	} rm;



	spinlock_t lock;

	struct mutex mutex;

};

drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/alloc/alloc_channel.h

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+161 −0
Original line number Diff line number Diff line 
#ifndef __src_common_sdk_nvidia_inc_alloc_alloc_channel_h__

#define __src_common_sdk_nvidia_inc_alloc_alloc_channel_h__

#include <nvrm/535.54.03/common/sdk/nvidia/inc/nvlimits.h>



/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */



/*

 * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

 * SPDX-License-Identifier: MIT

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

 * DEALINGS IN THE SOFTWARE.

 */



typedef struct NV_MEMORY_DESC_PARAMS {

    NV_DECLARE_ALIGNED(NvU64 base, 8);

    NV_DECLARE_ALIGNED(NvU64 size, 8);

    NvU32 addressSpace;

    NvU32 cacheAttrib;

} NV_MEMORY_DESC_PARAMS;



#define NVOS04_FLAGS_CHANNEL_TYPE                                  1:0

#define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL                         0x00000000

#define NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL                          0x00000001  // OBSOLETE

#define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL             0x00000002  // OBSOLETE



#define NVOS04_FLAGS_VPR                                           2:2

#define NVOS04_FLAGS_VPR_FALSE                                     0x00000000

#define NVOS04_FLAGS_VPR_TRUE                                      0x00000001



#define NVOS04_FLAGS_CC_SECURE                                     2:2

#define NVOS04_FLAGS_CC_SECURE_FALSE                               0x00000000

#define NVOS04_FLAGS_CC_SECURE_TRUE                                0x00000001



#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING                  3:3

#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE            0x00000000

#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE             0x00000001



#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE                       4:4

#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_DEFAULT               0x00000000

#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_ONE                   0x00000001



#define NVOS04_FLAGS_PRIVILEGED_CHANNEL                           5:5

#define NVOS04_FLAGS_PRIVILEGED_CHANNEL_FALSE                     0x00000000

#define NVOS04_FLAGS_PRIVILEGED_CHANNEL_TRUE                      0x00000001



#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING                     6:6

#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_FALSE               0x00000000

#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_TRUE                0x00000001



#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE                7:7

#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_FALSE          0x00000000

#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_TRUE           0x00000001



#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE                    10:8



#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED                    11:11

#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_FALSE              0x00000000

#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_TRUE               0x00000001



#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE               20:12



#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED               21:21

#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_FALSE         0x00000000

#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_TRUE          0x00000001



#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV                 22:22

#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_FALSE           0x00000000

#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_TRUE            0x00000001



#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER                        23:23

#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_FALSE                  0x00000000

#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_TRUE                   0x00000001



#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO                      24:24

#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_FALSE                0x00000000

#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_TRUE                 0x00000001



#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL           25:25

#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_FALSE     0x00000000

#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_TRUE      0x00000001



#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT                  26:26

#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_FALSE            0x00000000

#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_TRUE             0x00000001



#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT                 27:27

#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_FALSE           0x00000000

#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_TRUE            0x00000001



#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD                          29:28

#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_DEFAULT                  0x00000000

#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_ONE                      0x00000001

#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_TWO                      0x00000002



#define NVOS04_FLAGS_MAP_CHANNEL                                   30:30

#define NVOS04_FLAGS_MAP_CHANNEL_FALSE                             0x00000000

#define NVOS04_FLAGS_MAP_CHANNEL_TRUE                              0x00000001



#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC                          31:31

#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_FALSE                    0x00000000

#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_TRUE                     0x00000001



typedef struct NV_CHANNEL_ALLOC_PARAMS {



    NvHandle hObjectError; // error context DMA

    NvHandle hObjectBuffer; // no longer used

    NV_DECLARE_ALIGNED(NvU64 gpFifoOffset, 8);    // offset to beginning of GP FIFO

    NvU32    gpFifoEntries;    // number of GP FIFO entries



    NvU32    flags;





    NvHandle hContextShare; // context share handle

    NvHandle hVASpace; // VASpace for the channel



    // handle to UserD memory object for channel, ignored if hUserdMemory[0]=0

    NvHandle hUserdMemory[NV_MAX_SUBDEVICES];



    // offset to beginning of UserD within hUserdMemory[x]

    NV_DECLARE_ALIGNED(NvU64 userdOffset[NV_MAX_SUBDEVICES], 8);



    // engine type(NV2080_ENGINE_TYPE_*) with which this channel is associated

    NvU32    engineType;

    // Channel identifier that is unique for the duration of a RM session

    NvU32    cid;

    // One-hot encoded bitmask to match SET_SUBDEVICE_MASK methods

    NvU32    subDeviceId;

    NvHandle hObjectEccError; // ECC error context DMA



    NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS instanceMem, 8);

    NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS userdMem, 8);

    NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS ramfcMem, 8);

    NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS mthdbufMem, 8);



    NvHandle hPhysChannelGroup;              // reserved

    NvU32    internalFlags;                 // reserved

    NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS errorNotifierMem, 8); // reserved

    NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS eccErrorNotifierMem, 8); // reserved

    NvU32    ProcessID;                 // reserved

    NvU32    SubProcessID;                 // reserved

} NV_CHANNEL_ALLOC_PARAMS;



typedef NV_CHANNEL_ALLOC_PARAMS NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS;



#endif

drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/class/cl2080_notification.h

+20 −0
Original line number Diff line number Diff line
@@ -30,6 +30,26 @@ 


#define NV2080_NOTIFIERS_DP_IRQ                                    (7)



#define NV2080_ENGINE_TYPE_GRAPHICS                   (0x00000001)

#define NV2080_ENGINE_TYPE_GR0                        NV2080_ENGINE_TYPE_GRAPHICS



#define NV2080_ENGINE_TYPE_COPY0                      (0x00000009)



#define NV2080_ENGINE_TYPE_BSP                        (0x00000013)

#define NV2080_ENGINE_TYPE_NVDEC0                     NV2080_ENGINE_TYPE_BSP



#define NV2080_ENGINE_TYPE_MSENC                      (0x0000001b)

#define NV2080_ENGINE_TYPE_NVENC0                      NV2080_ENGINE_TYPE_MSENC  /* Mutually exclusive alias */



#define NV2080_ENGINE_TYPE_SW                         (0x00000022)



#define NV2080_ENGINE_TYPE_SEC2                       (0x00000026)



#define NV2080_ENGINE_TYPE_NVJPG                      (0x0000002b)

#define NV2080_ENGINE_TYPE_NVJPEG0                     NV2080_ENGINE_TYPE_NVJPG



#define NV2080_ENGINE_TYPE_OFA                        (0x00000033)



typedef struct {

    NvU32 plugDisplayMask;

    NvU32 unplugDisplayMask;

drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h

0 → 100644
+35 −0
Original line number Diff line number Diff line 
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080ce_h__

#define __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080ce_h__



/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */



/*

 * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

 * SPDX-License-Identifier: MIT

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

 * DEALINGS IN THE SOFTWARE.

 */



typedef struct NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS {

    NvU32 size;

} NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS;



#define NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE (0x20802a08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID" */



#endif

drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h

0 → 100644
+52 −0
Original line number Diff line number Diff line 
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080fifo_h__

#define __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080fifo_h__



/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */



/*

 * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

 * SPDX-License-Identifier: MIT

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

 * DEALINGS IN THE SOFTWARE.

 */



#define NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE                 (0x20801112) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */



#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES         32

#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES   16

#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA    2

#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN 16



typedef struct NV2080_CTRL_FIFO_DEVICE_ENTRY {

    NvU32 engineData[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES];

    NvU32 pbdmaIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA];

    NvU32 pbdmaFaultIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA];

    NvU32 numPbdmas;

    char  engineName[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN];

} NV2080_CTRL_FIFO_DEVICE_ENTRY;



typedef struct NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS {

    NvU32                         baseIndex;

    NvU32                         numEntries;

    NvBool                        bMore;

    // C form: NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES];

    NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES];

} NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS;



#endif