Commit 2aa5a6d9 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-7.0-2026-04-01' of... 

Merge tag 'amd-drm-fixes-7.0-2026-04-01' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-7.0-2026-04-01:

amdgpu:
- UserQ fixes
- PASID handling fix
- S4 fix for smu11 chips
- Misc small fixes

amdkfd:
- Non-4K page fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patch.msgid.link/20260401174731.3576021-1-alexander.deucher@amd.com
parents 7aaa8047 78746a47

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+6 −2
Original line number Diff line number Diff line
@@ -2703,8 +2703,12 @@ static int amdgpu_pmops_freeze(struct device *dev) 
	if (r)

		return r;



	if (amdgpu_acpi_should_gpu_reset(adev))

		return amdgpu_asic_reset(adev);

	if (amdgpu_acpi_should_gpu_reset(adev)) {

		amdgpu_device_lock_reset_domain(adev->reset_domain);

		r = amdgpu_asic_reset(adev);

		amdgpu_device_unlock_reset_domain(adev->reset_domain);

		return r;

	}

	return 0;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c

+44 −0
Original line number Diff line number Diff line
@@ -403,6 +403,50 @@ void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa, 
	drm_dev_exit(idx);

}



/**

 * amdgpu_gart_map_gfx9_mqd - map mqd and ctrl_stack dma_addresses into GART entries

 *

 * @adev: amdgpu_device pointer

 * @offset: offset into the GPU's gart aperture

 * @pages: number of pages to bind

 * @dma_addr: DMA addresses of pages

 * @flags: page table entry flags

 *

 * Map the MQD and control stack addresses into GART entries with the correct

 * memory types on gfxv9. The MQD occupies the first 4KB and is followed by

 * the control stack. The MQD uses UC (uncached) memory, while the control stack

 * uses NC (non-coherent) memory.

 */

void amdgpu_gart_map_gfx9_mqd(struct amdgpu_device *adev, uint64_t offset,

			int pages, dma_addr_t *dma_addr, uint64_t flags)

{

	uint64_t page_base;

	unsigned int i, j, t;

	int idx;

	uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_NC);

	void *dst;



	if (!adev->gart.ptr)

		return;



	if (!drm_dev_enter(adev_to_drm(adev), &idx))

		return;



	t = offset / AMDGPU_GPU_PAGE_SIZE;

	dst = adev->gart.ptr;

	for (i = 0; i < pages; i++) {

		page_base = dma_addr[i];

		for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {

			if ((i == 0) && (j == 0))

				amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags);

			else

				amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, ctrl_flags);

			page_base += AMDGPU_GPU_PAGE_SIZE;

		}

	}

	drm_dev_exit(idx);

}



/**

 * amdgpu_gart_bind - bind pages into the gart page table

 *

drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h

+2 −0
Original line number Diff line number Diff line
@@ -62,6 +62,8 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 
void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,

		     int pages, dma_addr_t *dma_addr, uint64_t flags,

		     void *dst);

void amdgpu_gart_map_gfx9_mqd(struct amdgpu_device *adev, uint64_t offset,

			int pages, dma_addr_t *dma_addr, uint64_t flags);

void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,

		      int pages, dma_addr_t *dma_addr, uint64_t flags);

void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa,

drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c

+4 −1
Original line number Diff line number Diff line
@@ -68,8 +68,11 @@ int amdgpu_pasid_alloc(unsigned int bits) 
		return -EINVAL;



	spin_lock(&amdgpu_pasid_idr_lock);

	/* TODO: Need to replace the idr with an xarry, and then

	 * handle the internal locking with ATOMIC safe paths.

	 */

	pasid = idr_alloc_cyclic(&amdgpu_pasid_idr, NULL, 1,

				 1U << bits, GFP_KERNEL);

				 1U << bits, GFP_ATOMIC);

	spin_unlock(&amdgpu_pasid_idr_lock);



	if (pasid >= 0)

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

+3 −13
Original line number Diff line number Diff line
@@ -853,25 +853,15 @@ static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev, 
	int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp);

	uint64_t page_idx, pages_per_xcc;

	int i;

	uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_NC);



	pages_per_xcc = total_pages;

	do_div(pages_per_xcc, num_xcc);



	for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) {

		/* MQD page: use default flags */

		amdgpu_gart_bind(adev,

		amdgpu_gart_map_gfx9_mqd(adev,

				gtt->offset + (page_idx << PAGE_SHIFT),

				1, &gtt->ttm.dma_address[page_idx], flags);

		/*

		 * Ctrl pages - modify the memory type to NC (ctrl_flags) from

		 * the second page of the BO onward.

		 */

		amdgpu_gart_bind(adev,

				gtt->offset + ((page_idx + 1) << PAGE_SHIFT),

				pages_per_xcc - 1,

				&gtt->ttm.dma_address[page_idx + 1],

				ctrl_flags);

				pages_per_xcc, &gtt->ttm.dma_address[page_idx],

				flags);

	}

}