Commit 2ac6a84b authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/reg: fix pipe conf, stat etc. register style 



Adhere to the style described at the top of i915_reg.h.

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/4360912222c8c0516d84253c3a05ef1cf421da01.1725974820.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 2575db50

drivers/gpu/drm/i915/i915_reg.h

+17 −15
Original line number Diff line number Diff line
@@ -1585,9 +1585,12 @@ 


/* Pipe A */

#define _PIPEADSL		0x70000

#define PIPEDSL(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)

#define   PIPEDSL_CURR_FIELD	REG_BIT(31) /* ctg+ */

#define   PIPEDSL_LINE_MASK	REG_GENMASK(19, 0)



#define _TRANSACONF		0x70008

#define TRANSCONF(dev_priv, trans)	_MMIO_PIPE2(dev_priv, (trans), _TRANSACONF)

#define   TRANSCONF_ENABLE			REG_BIT(31)

#define   TRANSCONF_DOUBLE_WIDE			REG_BIT(30) /* pre-i965 */

#define   TRANSCONF_STATE_ENABLE			REG_BIT(30) /* i965+ */
@@ -1647,6 +1650,7 @@ 
#define   TRANSCONF_PIXEL_COUNT_SCALING_X4	1



#define _PIPEASTAT		0x70024

#define PIPESTAT(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)

#define   PIPE_FIFO_UNDERRUN_STATUS		(1UL << 31)

#define   SPRITE1_FLIP_DONE_INT_EN_VLV		(1UL << 30)

#define   PIPE_CRC_ERROR_ENABLE			(1UL << 29)
@@ -1693,22 +1697,16 @@ 
#define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL << 1)

#define   PIPE_HBLANK_INT_STATUS		(1UL << 0)

#define   PIPE_OVERLAY_UPDATED_STATUS		(1UL << 0)



#define   PIPESTAT_INT_ENABLE_MASK		0x7fff0000

#define   PIPESTAT_INT_STATUS_MASK		0x0000ffff



#define TRANSCONF(dev_priv, trans)	_MMIO_PIPE2(dev_priv, (trans), _TRANSACONF)

#define PIPEDSL(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)

#define PIPEFRAME(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)

#define PIPEFRAMEPIXEL(dev_priv, pipe)	_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)

#define PIPESTAT(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)



#define _PIPE_ARB_CTL_A			0x70028 /* icl+ */

#define PIPE_ARB_CTL(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A)

#define   PIPE_ARB_USE_PROG_SLOTS	REG_BIT(13)



#define _PIPE_MISC_A			0x70030

#define _PIPE_MISC_B			0x71030

#define PIPE_MISC(pipe)			_MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B)

#define   PIPE_MISC_YUV420_ENABLE		REG_BIT(27) /* glk+ */

#define   PIPE_MISC_YUV420_MODE_FULL_BLEND	REG_BIT(26) /* glk+ */

#define   PIPE_MISC_HDR_MODE_PRECISION		REG_BIT(23) /* icl+ */
@@ -1736,16 +1734,15 @@ 
#define   PIPE_MISC_DITHER_TYPE_ST1		REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 1)

#define   PIPE_MISC_DITHER_TYPE_ST2		REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 2)

#define   PIPE_MISC_DITHER_TYPE_TEMP		REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 3)

#define PIPE_MISC(pipe)			_MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B)



#define _PIPE_MISC2_A					0x7002C

#define _PIPE_MISC2_B					0x7102C

#define PIPE_MISC2(pipe)		_MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B)

#define   PIPE_MISC2_BUBBLE_COUNTER_MASK	REG_GENMASK(31, 24)

#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN	REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)

#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS	REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)

#define   PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK		REG_GENMASK(2, 0) /* tgl+ */

#define   PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id)	REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))

#define PIPE_MISC2(pipe)		_MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B)



#define _ICL_PIPE_A_STATUS			0x70058

#define ICL_PIPESTATUS(dev_priv, pipe)			_MMIO_PIPE2(dev_priv, pipe, _ICL_PIPE_A_STATUS)
@@ -2068,33 +2065,38 @@ 
 *  frame = (high1 << 8) | low1;

 */

#define _PIPEAFRAMEHIGH          0x70040

#define PIPEFRAME(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)

#define   PIPE_FRAME_HIGH_MASK    0x0000ffff

#define   PIPE_FRAME_HIGH_SHIFT   0



#define _PIPEAFRAMEPIXEL         0x70044

#define PIPEFRAMEPIXEL(dev_priv, pipe)	_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)

#define   PIPE_FRAME_LOW_MASK     0xff000000

#define   PIPE_FRAME_LOW_SHIFT    24

#define   PIPE_PIXEL_MASK         0x00ffffff

#define   PIPE_PIXEL_SHIFT        0



/* GM45+ just has to be different */

#define _PIPEA_FRMCOUNT_G4X	0x70040

#define _PIPEA_FLIPCOUNT_G4X	0x70044

#define PIPE_FRMCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)



#define _PIPEA_FLIPCOUNT_G4X	0x70044

#define PIPE_FLIPCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X)



/* CHV pipe B blender */

#define _CHV_BLEND_A		0x60a00

#define CHV_BLEND(dev_priv, pipe)		_MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A)

#define   CHV_BLEND_MASK	REG_GENMASK(31, 30)

#define   CHV_BLEND_LEGACY	REG_FIELD_PREP(CHV_BLEND_MASK, 0)

#define   CHV_BLEND_ANDROID	REG_FIELD_PREP(CHV_BLEND_MASK, 1)

#define   CHV_BLEND_MPO		REG_FIELD_PREP(CHV_BLEND_MASK, 2)



#define _CHV_CANVAS_A		0x60a04

#define CHV_CANVAS(dev_priv, pipe)	_MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A)

#define   CHV_CANVAS_RED_MASK	REG_GENMASK(29, 20)

#define   CHV_CANVAS_GREEN_MASK	REG_GENMASK(19, 10)

#define   CHV_CANVAS_BLUE_MASK	REG_GENMASK(9, 0)



#define CHV_BLEND(dev_priv, pipe)		_MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A)

#define CHV_CANVAS(dev_priv, pipe)	_MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A)



/* Display/Sprite base address macros */

#define DISP_BASEADDR_MASK	(0xfffff000)

#define I915_LO_DISPBASE(val)	((val) & ~DISP_BASEADDR_MASK)