Commit 2ae20d65 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86_cache_for_v6.19_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 resource control updates from Borislav Petkov:

 - Add support for AMD's Smart Data Cache Injection feature which allows
   for direct insertion of data from I/O devices into the L3 cache, thus
   bypassing DRAM and saving its bandwidth; the resctrl side of the
   feature allows the size of the L3 used for data injection to be
   controlled

 - Add Intel Clearwater Forest to the list of CPUs which support
   Sub-NUMA clustering

 - Other fixes and cleanups

* tag 'x86_cache_for_v6.19_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  fs/resctrl: Update bit_usage to reflect io_alloc
  fs/resctrl: Introduce interface to modify io_alloc capacity bitmasks
  fs/resctrl: Modify struct rdt_parse_data to pass mode and CLOSID
  fs/resctrl: Introduce interface to display io_alloc CBMs
  fs/resctrl: Add user interface to enable/disable io_alloc feature
  fs/resctrl: Introduce interface to display "io_alloc" support
  x86,fs/resctrl: Implement "io_alloc" enable/disable handlers
  x86,fs/resctrl: Detect io_alloc feature
  x86/resctrl: Add SDCIAE feature in the command line options
  x86/cpufeatures: Add support for L3 Smart Data Cache Injection Allocation Enforcement
  fs/resctrl: Consider sparse masks when initializing new group's allocation
  x86/resctrl: Support Sub-NUMA Cluster (SNC) mode on Clearwater Forest
parents 2a47c26e ac7de456

Documentation/admin-guide/kernel-parameters.txt

+1 −1
Original line number Diff line number Diff line
@@ -6207,7 +6207,7 @@ 
	rdt=		[HW,X86,RDT]

			Turn on/off individual RDT features. List is:

			cmt, mbmtotal, mbmlocal, l3cat, l3cdp, l2cat, l2cdp,

			mba, smba, bmec, abmc.

			mba, smba, bmec, abmc, sdciae.

			E.g. to turn on cmt and turn off mba use:

				rdt=cmt,!mba

Documentation/filesystems/resctrl.rst

+109 −25
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ AMD refers to this feature as AMD Platform Quality of Service(AMD QoS). 
This feature is enabled by the CONFIG_X86_CPU_RESCTRL and the x86 /proc/cpuinfo

flag bits:



===============================================	================================

=============================================================== ================================

RDT (Resource Director Technology) Allocation			"rdt_a"

CAT (Cache Allocation Technology)				"cat_l3", "cat_l2"

CDP (Code and Data Prioritization)				"cdp_l3", "cdp_l2"
@@ -27,7 +27,8 @@ MBA (Memory Bandwidth Allocation) "mba" 
SMBA (Slow Memory Bandwidth Allocation)				""

BMEC (Bandwidth Monitoring Event Configuration)			""

ABMC (Assignable Bandwidth Monitoring Counters)			""

===============================================	================================

SDCIAE (Smart Data Cache Injection Allocation Enforcement)	""

=============================================================== ================================



Historically, new features were made visible by default in /proc/cpuinfo. This

resulted in the feature flags becoming hard to parse by humans. Adding a new
@@ -72,6 +73,11 @@ The 'info' directory contains information about the enabled 
resources. Each resource has its own subdirectory. The subdirectory

names reflect the resource names.



Most of the files in the resource's subdirectory are read-only, and

describe properties of the resource. Resources that support global

configuration options also include writable files that can be used

to modify those settings.



Each subdirectory contains the following files with respect to

allocation:
@@ -90,12 +96,19 @@ related to allocation: 
		must be set when writing a mask.



"shareable_bits":

		Bitmask of shareable resource with other executing

		entities (e.g. I/O). User can use this when

		setting up exclusive cache partitions. Note that

		some platforms support devices that have their

		own settings for cache use which can over-ride

		these bits.

		Bitmask of shareable resource with other executing entities

		(e.g. I/O). Applies to all instances of this resource. User

		can use this when setting up exclusive cache partitions.

		Note that some platforms support devices that have their

		own settings for cache use which can over-ride these bits.



		When "io_alloc" is enabled, a portion of each cache instance can

		be configured for shared use between hardware and software.

		"bit_usage" should be used to see which portions of each cache

		instance is configured for hardware use via "io_alloc" feature

		because every cache instance can have its "io_alloc" bitmask

		configured independently via "io_alloc_cbm".



"bit_usage":

		Annotated capacity bitmasks showing how all

		instances of the resource are used. The legend is:
@@ -109,16 +122,16 @@ related to allocation: 
			"H":

			      Corresponding region is used by hardware only

			      but available for software use. If a resource

			      has bits set in "shareable_bits" but not all

			      of these bits appear in the resource groups'

			      schematas then the bits appearing in

			      "shareable_bits" but no resource group will

			      be marked as "H".

			      has bits set in "shareable_bits" or "io_alloc_cbm"

			      but not all of these bits appear in the resource

			      groups' schemata then the bits appearing in

			      "shareable_bits" or "io_alloc_cbm" but no

			      resource group will be marked as "H".

			"X":

			      Corresponding region is available for sharing and

			      used by hardware and software. These are the

			      bits that appear in "shareable_bits" as

			      well as a resource group's allocation.

			      used by hardware and software. These are the bits

			      that appear in "shareable_bits" or "io_alloc_cbm"

			      as well as a resource group's allocation.

			"S":

			      Corresponding region is used by software

			      and available for sharing.
@@ -136,6 +149,77 @@ related to allocation: 
			"1":

			      Non-contiguous 1s value in CBM is supported.



"io_alloc":

		"io_alloc" enables system software to configure the portion of

		the cache allocated for I/O traffic. File may only exist if the

		system supports this feature on some of its cache resources.



			"disabled":

			      Resource supports "io_alloc" but the feature is disabled.

			      Portions of cache used for allocation of I/O traffic cannot

			      be configured.

			"enabled":

			      Portions of cache used for allocation of I/O traffic

			      can be configured using "io_alloc_cbm".

			"not supported":

			      Support not available for this resource.



		The feature can be modified by writing to the interface, for example:



		To enable::



			# echo 1 > /sys/fs/resctrl/info/L3/io_alloc



		To disable::



			# echo 0 > /sys/fs/resctrl/info/L3/io_alloc



		The underlying implementation may reduce resources available to

		general (CPU) cache allocation. See architecture specific notes

		below. Depending on usage requirements the feature can be enabled

		or disabled.



		On AMD systems, io_alloc feature is supported by the L3 Smart

		Data Cache Injection Allocation Enforcement (SDCIAE). The CLOSID for

		io_alloc is the highest CLOSID supported by the resource. When

		io_alloc is enabled, the highest CLOSID is dedicated to io_alloc and

		no longer available for general (CPU) cache allocation. When CDP is

		enabled, io_alloc routes I/O traffic using the highest CLOSID allocated

		for the instruction cache (CDP_CODE), making this CLOSID no longer

		available for general (CPU) cache allocation for both the CDP_CODE

		and CDP_DATA resources.



"io_alloc_cbm":

		Capacity bitmasks that describe the portions of cache instances to

		which I/O traffic from supported I/O devices are routed when "io_alloc"

		is enabled.



		CBMs are displayed in the following format:



			<cache_id0>=<cbm>;<cache_id1>=<cbm>;...



		Example::



			# cat /sys/fs/resctrl/info/L3/io_alloc_cbm

			0=ffff;1=ffff



		CBMs can be configured by writing to the interface.



		Example::



			# echo 1=ff > /sys/fs/resctrl/info/L3/io_alloc_cbm

			# cat /sys/fs/resctrl/info/L3/io_alloc_cbm

			0=ffff;1=00ff



			# echo "0=ff;1=f" > /sys/fs/resctrl/info/L3/io_alloc_cbm

			# cat /sys/fs/resctrl/info/L3/io_alloc_cbm

			0=00ff;1=000f



		When CDP is enabled "io_alloc_cbm" associated with the CDP_DATA and CDP_CODE

		resources may reflect the same values. For example, values read from and

		written to /sys/fs/resctrl/info/L3DATA/io_alloc_cbm may be reflected by

		/sys/fs/resctrl/info/L3CODE/io_alloc_cbm and vice versa.



Memory bandwidth(MB) subdirectory contains the following files

with respect to allocation:

arch/x86/include/asm/cpufeatures.h

+2 −0
Original line number Diff line number Diff line
@@ -500,6 +500,8 @@ 
#define X86_FEATURE_ABMC		(21*32+15) /* Assignable Bandwidth Monitoring Counters */

#define X86_FEATURE_MSR_IMM		(21*32+16) /* MSR immediate form instructions */



#define X86_FEATURE_SDCIAE		(21*32+18) /* L3 Smart Data Cache Injection Allocation Enforcement */



/*

 * BUG word(s)

 */

arch/x86/kernel/cpu/cpuid-deps.c

+1 −0
Original line number Diff line number Diff line
@@ -72,6 +72,7 @@ static const struct cpuid_dep cpuid_deps[] = { 
	{ X86_FEATURE_CQM_MBM_LOCAL,		X86_FEATURE_CQM_LLC   },

	{ X86_FEATURE_BMEC,			X86_FEATURE_CQM_MBM_TOTAL   },

	{ X86_FEATURE_BMEC,			X86_FEATURE_CQM_MBM_LOCAL   },

	{ X86_FEATURE_SDCIAE,			X86_FEATURE_CAT_L3    },

	{ X86_FEATURE_AVX512_BF16,		X86_FEATURE_AVX512VL  },

	{ X86_FEATURE_AVX512_FP16,		X86_FEATURE_AVX512BW  },

	{ X86_FEATURE_ENQCMD,			X86_FEATURE_XSAVES    },

arch/x86/kernel/cpu/resctrl/core.c

+9 −0
Original line number Diff line number Diff line
@@ -274,6 +274,11 @@ static void rdt_get_cdp_config(int level) 
	rdt_resources_all[level].r_resctrl.cdp_capable = true;

}



static void rdt_set_io_alloc_capable(struct rdt_resource *r)

{

	r->cache.io_alloc_capable = true;

}



static void rdt_get_cdp_l3_config(void)

{

	rdt_get_cdp_config(RDT_RESOURCE_L3);
@@ -719,6 +724,7 @@ enum { 
	RDT_FLAG_SMBA,

	RDT_FLAG_BMEC,

	RDT_FLAG_ABMC,

	RDT_FLAG_SDCIAE,

};



#define RDT_OPT(idx, n, f)	\
@@ -745,6 +751,7 @@ static struct rdt_options rdt_options[] __ro_after_init = { 
	RDT_OPT(RDT_FLAG_SMBA,	    "smba",	X86_FEATURE_SMBA),

	RDT_OPT(RDT_FLAG_BMEC,	    "bmec",	X86_FEATURE_BMEC),

	RDT_OPT(RDT_FLAG_ABMC,	    "abmc",	X86_FEATURE_ABMC),

	RDT_OPT(RDT_FLAG_SDCIAE,    "sdciae",	X86_FEATURE_SDCIAE),

};

#define NUM_RDT_OPTIONS ARRAY_SIZE(rdt_options)
@@ -853,6 +860,8 @@ static __init bool get_rdt_alloc_resources(void) 
		rdt_get_cache_alloc_cfg(1, r);

		if (rdt_cpu_has(X86_FEATURE_CDP_L3))

			rdt_get_cdp_l3_config();

		if (rdt_cpu_has(X86_FEATURE_SDCIAE))

			rdt_set_io_alloc_capable(r);

		ret = true;

	}

	if (rdt_cpu_has(X86_FEATURE_CAT_L2)) {