Unverified Commit 2afd1c20 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'v5.14-rockchip-drivers1' of... 

Merge tag 'v5.14-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/drivers

Yaml conversion of grf, pmu and power-domain bindings,
Power-domains for rk3568 + necessary plumbing,
Fixes for the usbphy bindings.

* tag 'v5.14-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  dt-bindings: soc: rockchip: drop unnecessary #phy-cells from grf.yaml
  dt-bindings: soc: rockchip: grf: add compatible for RK3308 USB grf
  dt-bindings: phy: rename phy nodename in phy-rockchip-inno-usb2.yaml
  dt-bindings: soc: rockchip: convert grf.txt to YAML
  soc: rockchip: power-domain: add rk3568 powerdomains
  dt-bindings: power: rockchip: Add bindings for RK3568 Soc
  dt-bindings: power: rockchip: Convert to json-schema
  dt-bindings: arm: rockchip: add more compatible strings to pmu.yaml
  dt-bindings: arm: rockchip: convert pmu.txt to YAML
  soc: rockchip: power-domain: Add a meaningful power domain name
  dt-bindings: add power-domain header for RK3568 SoCs

Link: https://lore.kernel.org/r/4647955.GXAFRqVoOG@phil


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 11548421 fcafd31b

Documentation/devicetree/bindings/arm/rockchip/pmu.txt

deleted100644 → 0
+0 −16
Original line number Diff line number Diff line 
Rockchip power-management-unit:

-------------------------------



The pmu is used to turn off and on different power domains of the SoCs

This includes the power to the CPU cores.



Required node properties:

- compatible value : = "rockchip,rk3066-pmu";

- reg : physical base address and the size of the registers window



Example:



	pmu@20004000 {

		compatible = "rockchip,rk3066-pmu";

		reg = <0x20004000 0x100>;

	};

Documentation/devicetree/bindings/arm/rockchip/pmu.yaml

0 → 100644
+55 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/rockchip/pmu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip Power Management Unit (PMU)



maintainers:

  - Elaine Zhang <zhangqing@rock-chips.com>

  - Heiko Stuebner <heiko@sntech.de>



description: |

  The PMU is used to turn on and off different power domains of the SoCs.

  This includes the power to the CPU cores.



select:

  properties:

    compatible:

      contains:

        enum:

          - rockchip,px30-pmu

          - rockchip,rk3066-pmu

          - rockchip,rk3288-pmu

          - rockchip,rk3399-pmu



  required:

    - compatible



properties:

  compatible:

    items:

      - enum:

          - rockchip,px30-pmu

          - rockchip,rk3066-pmu

          - rockchip,rk3288-pmu

          - rockchip,rk3399-pmu

      - const: syscon

      - const: simple-mfd



  reg:

    maxItems: 1



required:

  - compatible

  - reg



additionalProperties: true



examples:

  - |

    pmu@20004000 {

      compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";

      reg = <0x20004000 0x100>;

    };

Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml

+3 −8
Original line number Diff line number Diff line
@@ -29,9 +29,6 @@ properties: 
  "#clock-cells":

    const: 0



  "#phy-cells":

    const: 0



  clocks:

    maxItems: 1
@@ -119,7 +116,6 @@ required: 
  - reg

  - clock-output-names

  - "#clock-cells"

  - "#phy-cells"

  - host-port

  - otg-port
@@ -130,26 +126,25 @@ examples: 
    #include <dt-bindings/clock/rk3399-cru.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    u2phy0: usb2-phy@e450 {

    u2phy0: usb2phy@e450 {

      compatible = "rockchip,rk3399-usb2phy";

      reg = <0xe450 0x10>;

      clocks = <&cru SCLK_USB2PHY0_REF>;

      clock-names = "phyclk";

      clock-output-names = "clk_usbphy0_480m";

      #clock-cells = <0>;

      #phy-cells = <0>;



      u2phy0_host: host-port {

        #phy-cells = <0>;

        interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;

        interrupt-names = "linestate";

        #phy-cells = <0>;

      };



      u2phy0_otg: otg-port {

        #phy-cells = <0>;

        interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,

                     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,

                     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;

        interrupt-names = "otg-bvalid", "otg-id", "linestate";

        #phy-cells = <0>;

      };

    };

Documentation/devicetree/bindings/power/rockchip,power-controller.yaml

0 → 100644
+248 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip Power Domains



maintainers:

  - Elaine Zhang <zhangqing@rock-chips.com>

  - Heiko Stuebner <heiko@sntech.de>



description: |

  Rockchip processors include support for multiple power domains

  which can be powered up/down by software based on different

  application scenarios to save power.



  Power domains contained within power-controller node are

  generic power domain providers documented in

  Documentation/devicetree/bindings/power/power-domain.yaml.



  IP cores belonging to a power domain should contain a

  "power-domains" property that is a phandle for the

  power domain node representing the domain.



properties:

  $nodename:

    const: power-controller



  compatible:

    enum:

      - rockchip,px30-power-controller

      - rockchip,rk3036-power-controller

      - rockchip,rk3066-power-controller

      - rockchip,rk3128-power-controller

      - rockchip,rk3188-power-controller

      - rockchip,rk3228-power-controller

      - rockchip,rk3288-power-controller

      - rockchip,rk3328-power-controller

      - rockchip,rk3366-power-controller

      - rockchip,rk3368-power-controller

      - rockchip,rk3399-power-controller

      - rockchip,rk3568-power-controller



  "#power-domain-cells":

    const: 1



  "#address-cells":

    const: 1



  "#size-cells":

    const: 0



required:

  - compatible

  - "#power-domain-cells"



additionalProperties: false



patternProperties:

  "^power-domain@[0-9a-f]+$":



    $ref: "#/$defs/pd-node"



    unevaluatedProperties: false



    properties:

      "#address-cells":

        const: 1



      "#size-cells":

        const: 0



    patternProperties:

      "^power-domain@[0-9a-f]+$":



        $ref: "#/$defs/pd-node"



        unevaluatedProperties: false



        properties:

          "#address-cells":

            const: 1



          "#size-cells":

            const: 0



        patternProperties:

          "^power-domain@[0-9a-f]+$":



            $ref: "#/$defs/pd-node"



            unevaluatedProperties: false



            properties:

              "#power-domain-cells":

                const: 0



$defs:

  pd-node:

    type: object

    description: |

      Represents the power domains within the power controller node.



    properties:

      reg:

        maxItems: 1

        description: |

          Power domain index. Valid values are defined in

          "include/dt-bindings/power/px30-power.h"

          "include/dt-bindings/power/rk3036-power.h"

          "include/dt-bindings/power/rk3066-power.h"

          "include/dt-bindings/power/rk3128-power.h"

          "include/dt-bindings/power/rk3188-power.h"

          "include/dt-bindings/power/rk3228-power.h"

          "include/dt-bindings/power/rk3288-power.h"

          "include/dt-bindings/power/rk3328-power.h"

          "include/dt-bindings/power/rk3366-power.h"

          "include/dt-bindings/power/rk3368-power.h"

          "include/dt-bindings/power/rk3399-power.h"

          "include/dt-bindings/power/rk3568-power.h"



      clocks:

        minItems: 1

        maxItems: 30

        description: |

          A number of phandles to clocks that need to be enabled

          while power domain switches state.



      pm_qos:

        $ref: /schemas/types.yaml#/definitions/phandle-array

        description: |

          A number of phandles to qos blocks which need to be saved and restored

          while power domain switches state.



      "#power-domain-cells":

        enum: [0, 1]

        description:

          Must be 0 for nodes representing a single PM domain and 1 for nodes

          providing multiple PM domains.



    required:

      - reg

      - "#power-domain-cells"



examples:

  - |

    #include <dt-bindings/clock/rk3399-cru.h>

    #include <dt-bindings/power/rk3399-power.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        qos_hdcp: qos@ffa90000 {

            compatible = "rockchip,rk3399-qos", "syscon";

            reg = <0x0 0xffa90000 0x0 0x20>;

        };



        qos_iep: qos@ffa98000 {

            compatible = "rockchip,rk3399-qos", "syscon";

            reg = <0x0 0xffa98000 0x0 0x20>;

        };



        qos_rga_r: qos@ffab0000 {

            compatible = "rockchip,rk3399-qos", "syscon";

            reg = <0x0 0xffab0000 0x0 0x20>;

        };



        qos_rga_w: qos@ffab0080 {

            compatible = "rockchip,rk3399-qos", "syscon";

            reg = <0x0 0xffab0080 0x0 0x20>;

        };



        qos_video_m0: qos@ffab8000 {

            compatible = "rockchip,rk3399-qos", "syscon";

            reg = <0x0 0xffab8000 0x0 0x20>;

        };



        qos_video_m1_r: qos@ffac0000 {

            compatible = "rockchip,rk3399-qos", "syscon";

            reg = <0x0 0xffac0000 0x0 0x20>;

        };



        qos_video_m1_w: qos@ffac0080 {

            compatible = "rockchip,rk3399-qos", "syscon";

            reg = <0x0 0xffac0080 0x0 0x20>;

        };



        power-management@ff310000 {

            compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";

            reg = <0x0 0xff310000 0x0 0x1000>;



            power-controller {

                compatible = "rockchip,rk3399-power-controller";

                #power-domain-cells = <1>;

                #address-cells = <1>;

                #size-cells = <0>;



                /* These power domains are grouped by VD_CENTER */

                power-domain@RK3399_PD_IEP {

                    reg = <RK3399_PD_IEP>;

                    clocks = <&cru ACLK_IEP>,

                             <&cru HCLK_IEP>;

                    pm_qos = <&qos_iep>;

                    #power-domain-cells = <0>;

                };

                power-domain@RK3399_PD_RGA {

                    reg = <RK3399_PD_RGA>;

                    clocks = <&cru ACLK_RGA>,

                             <&cru HCLK_RGA>;

                    pm_qos = <&qos_rga_r>,

                             <&qos_rga_w>;

                    #power-domain-cells = <0>;

                };

                power-domain@RK3399_PD_VCODEC {

                    reg = <RK3399_PD_VCODEC>;

                    clocks = <&cru ACLK_VCODEC>,

                             <&cru HCLK_VCODEC>;

                    pm_qos = <&qos_video_m0>;

                    #power-domain-cells = <0>;

                };

                power-domain@RK3399_PD_VDU {

                    reg = <RK3399_PD_VDU>;

                    clocks = <&cru ACLK_VDU>,

                             <&cru HCLK_VDU>;

                    pm_qos = <&qos_video_m1_r>,

                             <&qos_video_m1_w>;

                    #power-domain-cells = <0>;

                };

                power-domain@RK3399_PD_VIO {

                    reg = <RK3399_PD_VIO>;

                    #power-domain-cells = <1>;

                    #address-cells = <1>;

                    #size-cells = <0>;



                    power-domain@RK3399_PD_HDCP {

                        reg = <RK3399_PD_HDCP>;

                        clocks = <&cru ACLK_HDCP>,

                                 <&cru HCLK_HDCP>,

                                 <&cru PCLK_HDCP>;

                        pm_qos = <&qos_hdcp>;

                        #power-domain-cells = <0>;

                    };

                };

            };

        };

    };

Documentation/devicetree/bindings/soc/rockchip/grf.txt

deleted100644 → 0
+0 −61
Original line number Diff line number Diff line 
* Rockchip General Register Files (GRF)



The general register file will be used to do static set by software, which

is composed of many registers for system control.



From RK3368 SoCs, the GRF is divided into two sections,

- GRF, used for general non-secure system,

- SGRF, used for general secure system,

- PMUGRF, used for always on system



On RK3328 SoCs, the GRF adds a section for USB2PHYGRF,



ON RK3308 SoC, the GRF is divided into four sections:

- GRF, used for general non-secure system,

- SGRF, used for general secure system,

- DETECTGRF, used for audio codec system,

- COREGRF, used for pvtm,



Required Properties:



- compatible: GRF should be one of the following:

   - "rockchip,px30-grf", "syscon": for px30

   - "rockchip,rk3036-grf", "syscon": for rk3036

   - "rockchip,rk3066-grf", "syscon": for rk3066

   - "rockchip,rk3188-grf", "syscon": for rk3188

   - "rockchip,rk3228-grf", "syscon": for rk3228

   - "rockchip,rk3288-grf", "syscon": for rk3288

   - "rockchip,rk3308-grf", "syscon": for rk3308

   - "rockchip,rk3328-grf", "syscon": for rk3328

   - "rockchip,rk3368-grf", "syscon": for rk3368

   - "rockchip,rk3399-grf", "syscon": for rk3399

   - "rockchip,rv1108-grf", "syscon": for rv1108

- compatible: DETECTGRF should be one of the following:

   - "rockchip,rk3308-detect-grf", "syscon": for rk3308

- compatilbe: COREGRF should be one of the following:

   - "rockchip,rk3308-core-grf", "syscon": for rk3308

- compatible: PMUGRF should be one of the following:

   - "rockchip,px30-pmugrf", "syscon": for px30

   - "rockchip,rk3368-pmugrf", "syscon": for rk3368

   - "rockchip,rk3399-pmugrf", "syscon": for rk3399

- compatible: SGRF should be one of the following:

   - "rockchip,rk3288-sgrf", "syscon": for rk3288

- compatible: USB2PHYGRF should be one of the following:

   - "rockchip,px30-usb2phy-grf", "syscon": for px30

   - "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328

- compatible: USBGRF should be one of the following:

   - "rockchip,rv1108-usbgrf", "syscon": for rv1108

- reg: physical base address of the controller and length of memory mapped

  region.



Example: GRF and PMUGRF of RK3399 SoCs



	pmugrf: syscon@ff320000 {

		compatible = "rockchip,rk3399-pmugrf", "syscon";

		reg = <0x0 0xff320000 0x0 0x1000>;

	};



	grf: syscon@ff770000 {

		compatible = "rockchip,rk3399-grf", "syscon";

		reg = <0x0 0xff770000 0x0 0x10000>;

	};