Commit 2b4e497c authored by Martin Tůma's avatar Martin Tůma Committed by Hans Verkuil
Browse files

media: admin-guide: mgb4: Outputs DV timings documentation update 



Properly document the function of the mgb4 output "frame_rate" sysfs
parameter and update the default DV timings values according to the latest
code changes.

Signed-off-by: default avatarMartin Tůma <martin.tuma@digiteqautomotive.com>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
parent e3582018

Documentation/admin-guide/media/mgb4.rst

+14 −9
Original line number Diff line number Diff line
@@ -227,8 +227,13 @@ Common FPDL3/GMSL output parameters 
    open.*



**frame_rate** (RW):

    Output video frame rate in frames per second. The default frame rate is

    60Hz.

    Output video signal frame rate limit in frames per second. Due to

    the limited output pixel clock steps, the card can not always generate

    a frame rate perfectly matching the value required by the connected display.

    Using this parameter one can limit the frame rate by "crippling" the signal

    so that the lines are not equal (the porches of the last line differ) but

    the signal appears like having the exact frame rate to the connected display.

    The default frame rate limit is 60Hz.



**hsync_polarity** (RW):

    HSYNC signal polarity.
@@ -253,33 +258,33 @@ Common FPDL3/GMSL output parameters 
    and there is a non-linear stepping between two consecutive allowed

    frequencies. The driver finds the nearest allowed frequency to the given

    value and sets it. When reading this property, you get the exact

    frequency set by the driver. The default frequency is 70000kHz.

    frequency set by the driver. The default frequency is 61150kHz.



    *Note: This parameter can not be changed while the output v4l2 device is

    open.*



**hsync_width** (RW):

    Width of the HSYNC signal in pixels. The default value is 16.

    Width of the HSYNC signal in pixels. The default value is 40.



**vsync_width** (RW):

    Width of the VSYNC signal in video lines. The default value is 2.

    Width of the VSYNC signal in video lines. The default value is 20.



**hback_porch** (RW):

    Number of PCLK pulses between deassertion of the HSYNC signal and the first

    valid pixel in the video line (marked by DE=1). The default value is 32.

    valid pixel in the video line (marked by DE=1). The default value is 50.



**hfront_porch** (RW):

    Number of PCLK pulses between the end of the last valid pixel in the video

    line (marked by DE=1) and assertion of the HSYNC signal. The default value

    is 32.

    is 50.



**vback_porch** (RW):

    Number of video lines between deassertion of the VSYNC signal and the video

    line with the first valid pixel (marked by DE=1). The default value is 2.

    line with the first valid pixel (marked by DE=1). The default value is 31.



**vfront_porch** (RW):

    Number of video lines between the end of the last valid pixel line (marked

    by DE=1) and assertion of the VSYNC signal. The default value is 2.

    by DE=1) and assertion of the VSYNC signal. The default value is 30.



FPDL3 specific input parameters

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~