Commit 2b7112ea authored by Alexander Stein's avatar Alexander Stein Committed by Shawn Guo
Browse files

arm64: dts: imx8qxp: Add audio clock mux node 



The audio clock mux (ACM) selects the input clock for each attached
consumer, referenced by clock-cell.

Signed-off-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: default avatarFrank Li <Frank.Li@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 951cd070

arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi

+59 −0
Original line number Diff line number Diff line
@@ -289,4 +289,63 @@ aud_pll_div1_lpcg: clock-controller@59d30000 { 
		clock-output-names = "aud_pll_div_clk1_lpcg_clk";

		power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>;

	};



	acm: acm@59e00000 {

		compatible = "fsl,imx8qxp-acm";

		reg = <0x59e00000 0x1d0000>;

		#clock-cells = <1>;

		power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,

				<&pd IMX_SC_R_AUDIO_CLK_1>,

				<&pd IMX_SC_R_MCLK_OUT_0>,

				<&pd IMX_SC_R_MCLK_OUT_1>,

				<&pd IMX_SC_R_AUDIO_PLL_0>,

				<&pd IMX_SC_R_AUDIO_PLL_1>,

				<&pd IMX_SC_R_ASRC_0>,

				<&pd IMX_SC_R_ASRC_1>,

				<&pd IMX_SC_R_ESAI_0>,

				<&pd IMX_SC_R_SAI_0>,

				<&pd IMX_SC_R_SAI_1>,

				<&pd IMX_SC_R_SAI_2>,

				<&pd IMX_SC_R_SAI_3>,

				<&pd IMX_SC_R_SAI_4>,

				<&pd IMX_SC_R_SAI_5>,

				<&pd IMX_SC_R_SPDIF_0>,

				<&pd IMX_SC_R_MQS_0>;

		clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>,

			 <&aud_rec1_lpcg IMX_LPCG_CLK_0>,

			 <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,

			 <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,

			 <&clk_ext_aud_mclk0>,

			 <&clk_ext_aud_mclk1>,

			 <&clk_esai0_rx_clk>,

			 <&clk_esai0_rx_hf_clk>,

			 <&clk_esai0_tx_clk>,

			 <&clk_esai0_tx_hf_clk>,

			 <&clk_spdif0_rx>,

			 <&clk_sai0_rx_bclk>,

			 <&clk_sai0_tx_bclk>,

			 <&clk_sai1_rx_bclk>,

			 <&clk_sai1_tx_bclk>,

			 <&clk_sai2_rx_bclk>,

			 <&clk_sai3_rx_bclk>,

			 <&clk_sai4_rx_bclk>;

		clock-names = "aud_rec_clk0_lpcg_clk",

			      "aud_rec_clk1_lpcg_clk",

			      "aud_pll_div_clk0_lpcg_clk",

			      "aud_pll_div_clk1_lpcg_clk",

			      "ext_aud_mclk0",

			      "ext_aud_mclk1",

			      "esai0_rx_clk",

			      "esai0_rx_hf_clk",

			      "esai0_tx_clk",

			      "esai0_tx_hf_clk",

			      "spdif0_rx",

			      "sai0_rx_bclk",

			      "sai0_tx_bclk",

			      "sai1_rx_bclk",

			      "sai1_tx_bclk",

			      "sai2_rx_bclk",

			      "sai3_rx_bclk",

			      "sai4_rx_bclk";

	};

};