Commit 2bbb5fe3 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Rob Clark
Browse files

drm/msm/a6xx: Store primFifoThreshold in struct a6xx_info 



The if-else monster is so unmaintainable that one case is repeated
twice. Get rid of it.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/611092/


[add missing entry to a615 catalog to resolve conflict]
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 1b3975ef

drivers/gpu/drm/msm/adreno/a6xx_catalog.c

+15 −0
Original line number Diff line number Diff line
@@ -636,6 +636,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a612_hwcg,

			.protect = &a630_protect,

			.prim_fifo_threshold = 0x00080000,

		},

		/*

		 * There are (at least) three SoCs implementing A610: SM6125
@@ -666,6 +667,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a615_hwcg,

			.protect = &a630_protect,

			.prim_fifo_threshold = 0x0018000,

		},

		.speedbins = ADRENO_SPEEDBINS(

			/*
@@ -694,6 +696,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a615_hwcg,

			.protect = &a630_protect,

			.prim_fifo_threshold = 0x00180000,

		},

		.speedbins = ADRENO_SPEEDBINS(

			{ 0,   0 },
@@ -716,6 +719,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.init = a6xx_gpu_init,

		.a6xx = &(const struct a6xx_info) {

			.protect = &a630_protect,

			.prim_fifo_threshold = 0x00180000,

		},

		.speedbins = ADRENO_SPEEDBINS(

			{ 0,   0 },
@@ -738,6 +742,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a615_hwcg,

			.protect = &a630_protect,

			.prim_fifo_threshold = 0x00018000,

		},

		.speedbins = ADRENO_SPEEDBINS(

			{ 0,   0 },
@@ -760,6 +765,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a615_hwcg,

			.protect = &a630_protect,

			.prim_fifo_threshold = 0x00018000,

		},

		.speedbins = ADRENO_SPEEDBINS(

			{ 0,   0 },
@@ -782,6 +788,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a615_hwcg,

			.protect = &a630_protect,

			.prim_fifo_threshold = 0x00018000,

		},

		.speedbins = ADRENO_SPEEDBINS(

			{ 0,   0 },
@@ -809,6 +816,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a630_hwcg,

			.protect = &a630_protect,

			.prim_fifo_threshold = 0x00180000,

		},

	}, {

		.chip_ids = ADRENO_CHIP_IDS(0x06040001),
@@ -826,6 +834,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a640_hwcg,

			.protect = &a630_protect,

			.prim_fifo_threshold = 0x00180000,

		},

		.speedbins = ADRENO_SPEEDBINS(

			{ 0, 0 },
@@ -848,6 +857,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a650_hwcg,

			.protect = &a650_protect,

			.prim_fifo_threshold = 0x00300200,

		},

		.address_space_size = SZ_16G,

		.speedbins = ADRENO_SPEEDBINS(
@@ -873,6 +883,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a660_hwcg,

			.protect = &a660_protect,

			.prim_fifo_threshold = 0x00300200,

		},

		.address_space_size = SZ_16G,

	}, {
@@ -891,6 +902,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a660_hwcg,

			.protect = &a660_protect,

			.prim_fifo_threshold = 0x00200200,

		},

		.address_space_size = SZ_16G,

		.speedbins = ADRENO_SPEEDBINS(
@@ -916,6 +928,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a640_hwcg,

			.protect = &a630_protect,

			.prim_fifo_threshold = 0x00200200,

		},

	}, {

		.chip_ids = ADRENO_CHIP_IDS(0x06090000),
@@ -933,6 +946,7 @@ static const struct adreno_info a6xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a690_hwcg,

			.protect = &a690_protect,

			.prim_fifo_threshold = 0x00800200,

		},

		.address_space_size = SZ_16G,

	}
@@ -1193,6 +1207,7 @@ static const struct adreno_info a7xx_gpus[] = { 
		.a6xx = &(const struct a6xx_info) {

			.hwcg = a702_hwcg,

			.protect = &a650_protect,

			.prim_fifo_threshold = 0x0000c000,

		},

		.speedbins = ADRENO_SPEEDBINS(

			{ 0,   0 },

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+5 −19
Original line number Diff line number Diff line
@@ -981,25 +981,11 @@ static int hw_init(struct msm_gpu *gpu) 
	} else if (!adreno_is_a7xx(adreno_gpu))

		gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);



	/* Setting the primFifo thresholds default values,

	 * and vccCacheSkipDis=1 bit (0x200) for A640 and newer

	*/

	if (adreno_is_a702(adreno_gpu))

		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x0000c000);

	else if (adreno_is_a690(adreno_gpu))

		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00800200);

	else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))

		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);

	else if (adreno_is_a640_family(adreno_gpu) || adreno_is_7c3(adreno_gpu))

		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);

	else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))

		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);

	else if (adreno_is_a619(adreno_gpu))

		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00018000);

	else if (adreno_is_a610(adreno_gpu))

		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000);

	else if (!adreno_is_a7xx(adreno_gpu))

		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000);



	/* Set the default primFifo threshold values */

	if (adreno_gpu->info->a6xx->prim_fifo_threshold)

		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL,

			  adreno_gpu->info->a6xx->prim_fifo_threshold);



	/* Set the AHB default slave response to "ERROR" */

	gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ struct a6xx_info { 
	const struct adreno_reglist *hwcg;

	const struct adreno_protect *protect;

	u32 gmu_chipid;

	u32 prim_fifo_threshold;

};



struct a6xx_gpu {