Commit 2be189c9 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Relocate vlv_wait_port_ready() 



While vlv_wait_port_ready() doens't directly talk to the VLV/CHV
DPIO PHY, the signals it's looking for do come from the PHY. So
it seems appropriate to relocate it into intel_dpio_phy.c.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250213150220.13580-8-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 7105bf94

drivers/gpu/drm/i915/display/intel_display.c

+0 −34
Original line number Diff line number Diff line
@@ -473,40 +473,6 @@ static void assert_planes_disabled(struct intel_crtc *crtc) 
		assert_plane_disabled(plane);

}



void vlv_wait_port_ready(struct intel_display *display,

			 struct intel_digital_port *dig_port,

			 unsigned int expected_mask)

{

	u32 port_mask;

	i915_reg_t dpll_reg;



	switch (dig_port->base.port) {

	default:

		MISSING_CASE(dig_port->base.port);

		fallthrough;

	case PORT_B:

		port_mask = DPLL_PORTB_READY_MASK;

		dpll_reg = DPLL(display, 0);

		break;

	case PORT_C:

		port_mask = DPLL_PORTC_READY_MASK;

		dpll_reg = DPLL(display, 0);

		expected_mask <<= 4;

		break;

	case PORT_D:

		port_mask = DPLL_PORTD_READY_MASK;

		dpll_reg = DPIO_PHY_STATUS;

		break;

	}



	if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000))

		drm_WARN(display->drm, 1,

			 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",

			 dig_port->base.base.base.id, dig_port->base.base.name,

			 intel_de_read(display, dpll_reg) & port_mask,

			 expected_mask);

}



void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)

{

	struct intel_display *display = to_intel_display(new_crtc_state);

drivers/gpu/drm/i915/display/intel_display.h

+0 −3
Original line number Diff line number Diff line
@@ -486,9 +486,6 @@ bool intel_encoder_is_tc(struct intel_encoder *encoder); 
enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder);



int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);

void vlv_wait_port_ready(struct intel_display *display,

			 struct intel_digital_port *dig_port,

			 unsigned int expected_mask);



bool intel_fuzzy_clock_check(int clock1, int clock2);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

+34 −0
Original line number Diff line number Diff line
@@ -1156,3 +1156,37 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder, 
	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060);

	vlv_dpio_put(dev_priv);

}



void vlv_wait_port_ready(struct intel_display *display,

			 struct intel_digital_port *dig_port,

			 unsigned int expected_mask)

{

	u32 port_mask;

	i915_reg_t dpll_reg;



	switch (dig_port->base.port) {

	default:

		MISSING_CASE(dig_port->base.port);

		fallthrough;

	case PORT_B:

		port_mask = DPLL_PORTB_READY_MASK;

		dpll_reg = DPLL(display, 0);

		break;

	case PORT_C:

		port_mask = DPLL_PORTC_READY_MASK;

		dpll_reg = DPLL(display, 0);

		expected_mask <<= 4;

		break;

	case PORT_D:

		port_mask = DPLL_PORTD_READY_MASK;

		dpll_reg = DPIO_PHY_STATUS;

		break;

	}



	if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000))

		drm_WARN(display->drm, 1,

			 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",

			 dig_port->base.base.base.id, dig_port->base.base.name,

			 intel_de_read(display, dpll_reg) & port_mask,

			 expected_mask);

}

drivers/gpu/drm/i915/display/intel_dpio_phy.h

+8 −0
Original line number Diff line number Diff line
@@ -72,6 +72,9 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, 
				const struct intel_crtc_state *crtc_state);

void vlv_phy_reset_lanes(struct intel_encoder *encoder,

			 const struct intel_crtc_state *old_crtc_state);

void vlv_wait_port_ready(struct intel_display *display,

			 struct intel_digital_port *dig_port,

			 unsigned int expected_mask);

#else

static inline void bxt_port_to_phy_channel(struct intel_display *display, enum port port,

					   enum dpio_phy *phy, enum dpio_channel *ch)
@@ -170,6 +173,11 @@ static inline void vlv_phy_reset_lanes(struct intel_encoder *encoder, 
				       const struct intel_crtc_state *old_crtc_state)

{

}

static inline void vlv_wait_port_ready(struct intel_display *display,

				       struct intel_digital_port *dig_port,

				       unsigned int expected_mask)

{

}

#endif



#endif /* __INTEL_DPIO_PHY_H__ */