Commit 2c0410fb authored by YiPeng Chai's avatar YiPeng Chai Committed by Alex Deucher
Browse files

rm/amdgpu: Remove unused code 



Remove unused code.

Signed-off-by: default avatarYiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ebbc2ada

drivers/gpu/drm/amd/amdgpu/umc_v12_0.c

+0 −71
Original line number Diff line number Diff line
@@ -376,77 +376,6 @@ static int umc_v12_0_err_cnt_init_per_channel(struct amdgpu_device *adev, 
	return 0;

}



#ifdef TO_BE_REMOVED

static void umc_v12_0_ecc_info_query_ras_error_count(struct amdgpu_device *adev,

					void *ras_error_status)

{

	struct ras_query_context qctx;



	memset(&qctx, 0, sizeof(qctx));

	qctx.event_id = amdgpu_ras_acquire_event_id(adev, amdgpu_ras_intr_triggered() ?

						    RAS_EVENT_TYPE_ISR : RAS_EVENT_TYPE_INVALID);



	amdgpu_mca_smu_log_ras_error(adev,

		AMDGPU_RAS_BLOCK__UMC, AMDGPU_MCA_ERROR_TYPE_CE, ras_error_status, &qctx);

	amdgpu_mca_smu_log_ras_error(adev,

		AMDGPU_RAS_BLOCK__UMC, AMDGPU_MCA_ERROR_TYPE_UE, ras_error_status, &qctx);

}



static void umc_v12_0_ecc_info_query_ras_error_address(struct amdgpu_device *adev,

					void *ras_error_status)

{

	struct ras_err_node *err_node;

	uint64_t mc_umc_status;

	struct ras_err_info *err_info;

	struct ras_err_addr *mca_err_addr, *tmp;

	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;

	struct ta_ras_query_address_input addr_in;



	for_each_ras_error(err_node, err_data) {

		err_info = &err_node->err_info;

		if (list_empty(&err_info->err_addr_list))

			continue;



		addr_in.ma.node_inst = err_info->mcm_info.die_id;

		addr_in.ma.socket_id = err_info->mcm_info.socket_id;



		list_for_each_entry_safe(mca_err_addr, tmp, &err_info->err_addr_list, node) {

			mc_umc_status = mca_err_addr->err_status;

			if (mc_umc_status &&

				(umc_v12_0_is_uncorrectable_error(adev, mc_umc_status) ||

				 umc_v12_0_is_deferred_error(adev, mc_umc_status))) {

				uint64_t mca_addr, err_addr, mca_ipid;

				uint32_t InstanceIdLo;



				mca_addr = mca_err_addr->err_addr;

				mca_ipid = mca_err_addr->err_ipid;



				err_addr = REG_GET_FIELD(mca_addr,

							MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);

				InstanceIdLo = REG_GET_FIELD(mca_ipid, MCMP1_IPIDT0, InstanceIdLo);



				addr_in.ma.err_addr = err_addr;

				addr_in.ma.ch_inst = MCA_IPID_LO_2_UMC_CH(InstanceIdLo);

				addr_in.ma.umc_inst = MCA_IPID_LO_2_UMC_INST(InstanceIdLo);



				dev_info(adev->dev, "UMC:IPID:0x%llx, aid:%d, inst:%d, ch:%d, err_addr:0x%llx\n",

					mca_ipid,

					err_info->mcm_info.die_id,

					MCA_IPID_LO_2_UMC_INST(InstanceIdLo),

					MCA_IPID_LO_2_UMC_CH(InstanceIdLo),

					err_addr);



				umc_v12_0_convert_error_address(adev,

					err_data, &addr_in);

			}



			/* Delete error address node from list and free memory */

			amdgpu_ras_del_mca_err_addr(err_info, mca_err_addr);

		}

	}

}

#endif



static bool umc_v12_0_check_ecc_err_status(struct amdgpu_device *adev,

			enum amdgpu_mca_error_type type, void *ras_error_status)

{