Commit 2c088345 authored by Damon Ding's avatar Damon Ding Committed by Dmitry Baryshkov
Browse files

drm/bridge: analogix_dp: Add support for phy configuration. 



Add support to configurate link rate, lane count, voltage swing and
pre-emphasis with phy_configure(). It is helpful in application scenarios
where analogix controller is mixed with the phy of other vendors.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarDamon Ding <damon.ding@rock-chips.com>
Link: https://lore.kernel.org/r/20250310104114.2608063-4-damon.ding@rock-chips.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
parent c71db051

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

+1 −0
Original line number Diff line number Diff line
@@ -1680,6 +1680,7 @@ int analogix_dp_resume(struct analogix_dp_device *dp) 
	if (dp->plat_data->power_on)

		dp->plat_data->power_on(dp->plat_data);



	phy_set_mode(dp->phy, PHY_MODE_DP);

	phy_power_on(dp->phy);



	analogix_dp_init_dp(dp);

drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c

+52 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include <linux/gpio/consumer.h>

#include <linux/io.h>

#include <linux/iopoll.h>

#include <linux/phy/phy.h>



#include <drm/bridge/analogix_dp.h>
@@ -513,10 +514,24 @@ void analogix_dp_enable_sw_function(struct analogix_dp_device *dp) 
void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)

{

	u32 reg;

	int ret;



	reg = bwtype;

	if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62))

		writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET);



	if (dp->phy) {

		union phy_configure_opts phy_cfg = {0};



		phy_cfg.dp.link_rate =

			drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100;

		phy_cfg.dp.set_rate = true;

		ret = phy_configure(dp->phy, &phy_cfg);

		if (ret && ret != -EOPNOTSUPP) {

			dev_err(dp->dev, "%s: phy_configure() failed: %d\n", __func__, ret);

			return;

		}

	}

}



void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
@@ -530,9 +545,22 @@ void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype) 
void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)

{

	u32 reg;

	int ret;



	reg = count;

	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);



	if (dp->phy) {

		union phy_configure_opts phy_cfg = {0};



		phy_cfg.dp.lanes = dp->link_train.lane_count;

		phy_cfg.dp.set_lanes = true;

		ret = phy_configure(dp->phy, &phy_cfg);

		if (ret && ret != -EOPNOTSUPP) {

			dev_err(dp->dev, "%s: phy_configure() failed: %d\n", __func__, ret);

			return;

		}

	}

}



void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
@@ -546,10 +574,34 @@ void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count) 
void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp)

{

	u8 lane;

	int ret;



	for (lane = 0; lane < dp->link_train.lane_count; lane++)

		writel(dp->link_train.training_lane[lane],

		       dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane);



	if (dp->phy) {

		union phy_configure_opts phy_cfg = {0};



		for (lane = 0; lane < dp->link_train.lane_count; lane++) {

			u8 training_lane = dp->link_train.training_lane[lane];

			u8 vs, pe;



			vs = (training_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >>

			     DP_TRAIN_VOLTAGE_SWING_SHIFT;

			pe = (training_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >>

			     DP_TRAIN_PRE_EMPHASIS_SHIFT;

			phy_cfg.dp.voltage[lane] = vs;

			phy_cfg.dp.pre[lane] = pe;

		}



		phy_cfg.dp.set_voltages = true;

		ret = phy_configure(dp->phy, &phy_cfg);

		if (ret && ret != -EOPNOTSUPP) {

			dev_err(dp->dev, "%s: phy_configure() failed: %d\n", __func__, ret);

			return;

		}

	}

}



u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane)