Commit 2c14119a authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge tag 'linux-can-next-for-6.12-20240806' of... 

Merge tag 'linux-can-next-for-6.12-20240806' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next

Marc Kleine-Budde says:

====================
pull-request: can-next 2024-08-06

The first patch is by Frank Li and adds the can-transceiver property
to the flexcan device-tree bindings.

Haibo Chen contributes 2 patches for the flexcan driver to add wakeup
support for the imx95.

The 2 patches by Stefan Mätje for the esd_402_pci driver clean up the
driver and add support for the one-shot mode.

The last 15 patches are by Jimmy Assarsson and add hardware timestamp
support for all devices covered by the kvaser_usb driver.

* tag 'linux-can-next-for-6.12-20240806' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next:
  can: kvaser_usb: Rename kvaser_usb_{ethtool,netdev}_ops_hwts to kvaser_usb_{ethtool,netdev}_ops
  can: kvaser_usb: Remove struct variables kvaser_usb_{ethtool,netdev}_ops
  can: kvaser_usb: Remove KVASER_USB_QUIRK_HAS_HARDWARE_TIMESTAMP
  can: kvaser_usb: leaf: Add hardware timestamp support to usbcan devices
  can: kvaser_usb: leaf: Store MSB of timestamp
  can: kvaser_usb: leaf: Add structs for Tx ACK and clock overflow commands
  can: kvaser_usb: leaf: Add hardware timestamp support to leaf based devices
  can: kvaser_usb: leaf: kvaser_usb_leaf_tx_acknowledge: Rename local variable
  can: kvaser_usb: leaf: Replace kvaser_usb_leaf_m32c_dev_cfg with kvaser_usb_leaf_m32c_dev_cfg_{16,24,32}mhz
  can: kvaser_usb: leaf: Assign correct timestamp_freq for kvaser_usb_leaf_imx_dev_cfg_{16,24,32}mhz
  can: kvaser_usb: leaf: Add struct for Tx ACK commands
  can: kvaser_usb: hydra: Set hardware timestamp on transmitted packets
  can: kvaser_usb: hydra: Add struct for Tx ACK commands
  can: kvaser_usb: hydra: kvaser_usb_hydra_ktime_from_rx_cmd: Drop {rx_} in function name
  can: kvaser_usb: Add helper functions to convert device timestamp into ktime
  can: esd_402_pci: Add support for one-shot mode
  can: esd_402_pci: Rename esdACC CTRL register macros
  can: flexcan: add wakeup support for imx95
  dt-bindings: can: fsl,flexcan: move fsl,imx95-flexcan standalone
  dt-bindings: can: fsl,flexcan: add common 'can-transceiver' for fsl,flexcan
====================

Link: https://patch.msgid.link/20240806074731.1905378-1-mkl@pengutronix.de


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents acd221a6 fa3c40b9

Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml

+5 −3
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ properties: 
  compatible:

    oneOf:

      - enum:

          - fsl,imx95-flexcan

          - fsl,imx93-flexcan

          - fsl,imx8qm-flexcan

          - fsl,imx8mp-flexcan
@@ -38,9 +39,6 @@ properties: 
              - fsl,imx6ul-flexcan

              - fsl,imx6sx-flexcan

          - const: fsl,imx6q-flexcan

      - items:

          - const: fsl,imx95-flexcan

          - const: fsl,imx93-flexcan

      - items:

          - enum:

              - fsl,ls1028ar1-flexcan
@@ -80,6 +78,10 @@ properties: 
      node then controller is assumed to be little endian. If this property is

      present then controller is assumed to be big endian.



  can-transceiver:

    $ref: can-transceiver.yaml#

    unevaluatedProperties: false



  fsl,stop-mode:

    description: |

      Register bits of stop mode control.

drivers/net/can/esd/esd_402_pci-core.c

+3 −2
Original line number Diff line number Diff line
@@ -369,12 +369,13 @@ static int pci402_init_cores(struct pci_dev *pdev) 
		SET_NETDEV_DEV(netdev, &pdev->dev);



		priv = netdev_priv(netdev);

		priv->can.clock.freq = card->ov.core_frequency;

		priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |

			CAN_CTRLMODE_LISTENONLY |

			CAN_CTRLMODE_BERR_REPORTING |

			CAN_CTRLMODE_CC_LEN8_DLC;



		priv->can.clock.freq = card->ov.core_frequency;

		if (card->ov.features & ACC_OV_REG_FEAT_MASK_DAR)

			priv->can.ctrlmode_supported |= CAN_CTRLMODE_ONE_SHOT;

		if (card->ov.features & ACC_OV_REG_FEAT_MASK_CANFD)

			priv->can.bittiming_const = &pci402_bittiming_const_canfd;

		else

drivers/net/can/esd/esdacc.c

+30 −25
Original line number Diff line number Diff line
@@ -17,6 +17,9 @@ 
/* esdACC DLC register layout */

#define ACC_DLC_DLC_MASK GENMASK(3, 0)

#define ACC_DLC_RTR_FLAG BIT(4)

#define ACC_DLC_SSTX_FLAG BIT(24)	/* Single Shot TX */



/* esdACC DLC in struct acc_bmmsg_rxtxdone::acc_dlc.len only! */

#define ACC_DLC_TXD_FLAG BIT(5)



/* ecc value of esdACC equals SJA1000's ECC register */
@@ -43,8 +46,8 @@ 


static void acc_resetmode_enter(struct acc_core *core)

{

	acc_set_bits(core, ACC_CORE_OF_CTRL_MODE,

		     ACC_REG_CONTROL_MASK_MODE_RESETMODE);

	acc_set_bits(core, ACC_CORE_OF_CTRL,

		     ACC_REG_CTRL_MASK_RESETMODE);



	/* Read back reset mode bit to flush PCI write posting */

	acc_resetmode_entered(core);
@@ -52,14 +55,14 @@ static void acc_resetmode_enter(struct acc_core *core) 


static void acc_resetmode_leave(struct acc_core *core)

{

	acc_clear_bits(core, ACC_CORE_OF_CTRL_MODE,

		       ACC_REG_CONTROL_MASK_MODE_RESETMODE);

	acc_clear_bits(core, ACC_CORE_OF_CTRL,

		       ACC_REG_CTRL_MASK_RESETMODE);



	/* Read back reset mode bit to flush PCI write posting */

	acc_resetmode_entered(core);

}



static void acc_txq_put(struct acc_core *core, u32 acc_id, u8 acc_dlc,

static void acc_txq_put(struct acc_core *core, u32 acc_id, u32 acc_dlc,

			const void *data)

{

	acc_write32_noswap(core, ACC_CORE_OF_TXFIFO_DATA_1,
@@ -172,7 +175,7 @@ int acc_open(struct net_device *netdev) 
	struct acc_net_priv *priv = netdev_priv(netdev);

	struct acc_core *core = priv->core;

	u32 tx_fifo_status;

	u32 ctrl_mode;

	u32 ctrl;

	int err;



	/* Retry to enter RESET mode if out of sync. */
@@ -187,19 +190,19 @@ int acc_open(struct net_device *netdev) 
	if (err)

		return err;



	ctrl_mode = ACC_REG_CONTROL_MASK_IE_RXTX |

			ACC_REG_CONTROL_MASK_IE_TXERROR |

			ACC_REG_CONTROL_MASK_IE_ERRWARN |

			ACC_REG_CONTROL_MASK_IE_OVERRUN |

			ACC_REG_CONTROL_MASK_IE_ERRPASS;

	ctrl = ACC_REG_CTRL_MASK_IE_RXTX |

		ACC_REG_CTRL_MASK_IE_TXERROR |

		ACC_REG_CTRL_MASK_IE_ERRWARN |

		ACC_REG_CTRL_MASK_IE_OVERRUN |

		ACC_REG_CTRL_MASK_IE_ERRPASS;



	if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)

		ctrl_mode |= ACC_REG_CONTROL_MASK_IE_BUSERR;

		ctrl |= ACC_REG_CTRL_MASK_IE_BUSERR;



	if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)

		ctrl_mode |= ACC_REG_CONTROL_MASK_MODE_LOM;

		ctrl |= ACC_REG_CTRL_MASK_LOM;



	acc_set_bits(core, ACC_CORE_OF_CTRL_MODE, ctrl_mode);

	acc_set_bits(core, ACC_CORE_OF_CTRL, ctrl);



	acc_resetmode_leave(core);

	priv->can.state = CAN_STATE_ERROR_ACTIVE;
@@ -218,13 +221,13 @@ int acc_close(struct net_device *netdev) 
	struct acc_net_priv *priv = netdev_priv(netdev);

	struct acc_core *core = priv->core;



	acc_clear_bits(core, ACC_CORE_OF_CTRL_MODE,

		       ACC_REG_CONTROL_MASK_IE_RXTX |

		       ACC_REG_CONTROL_MASK_IE_TXERROR |

		       ACC_REG_CONTROL_MASK_IE_ERRWARN |

		       ACC_REG_CONTROL_MASK_IE_OVERRUN |

		       ACC_REG_CONTROL_MASK_IE_ERRPASS |

		       ACC_REG_CONTROL_MASK_IE_BUSERR);

	acc_clear_bits(core, ACC_CORE_OF_CTRL,

		       ACC_REG_CTRL_MASK_IE_RXTX |

		       ACC_REG_CTRL_MASK_IE_TXERROR |

		       ACC_REG_CTRL_MASK_IE_ERRWARN |

		       ACC_REG_CTRL_MASK_IE_OVERRUN |

		       ACC_REG_CTRL_MASK_IE_ERRPASS |

		       ACC_REG_CTRL_MASK_IE_BUSERR);



	netif_stop_queue(netdev);

	acc_resetmode_enter(core);
@@ -233,9 +236,9 @@ int acc_close(struct net_device *netdev) 
	/* Mark pending TX requests to be aborted after controller restart. */

	acc_write32(core, ACC_CORE_OF_TX_ABORT_MASK, 0xffff);



	/* ACC_REG_CONTROL_MASK_MODE_LOM is only accessible in RESET mode */

	acc_clear_bits(core, ACC_CORE_OF_CTRL_MODE,

		       ACC_REG_CONTROL_MASK_MODE_LOM);

	/* ACC_REG_CTRL_MASK_LOM is only accessible in RESET mode */

	acc_clear_bits(core, ACC_CORE_OF_CTRL,

		       ACC_REG_CTRL_MASK_LOM);



	close_candev(netdev);

	return 0;
@@ -249,7 +252,7 @@ netdev_tx_t acc_start_xmit(struct sk_buff *skb, struct net_device *netdev) 
	u8 tx_fifo_head = core->tx_fifo_head;

	int fifo_usage;

	u32 acc_id;

	u8 acc_dlc;

	u32 acc_dlc;



	if (can_dropped_invalid_skb(netdev, skb))

		return NETDEV_TX_OK;
@@ -274,6 +277,8 @@ netdev_tx_t acc_start_xmit(struct sk_buff *skb, struct net_device *netdev) 
	acc_dlc = can_get_cc_dlc(cf, priv->can.ctrlmode);

	if (cf->can_id & CAN_RTR_FLAG)

		acc_dlc |= ACC_DLC_RTR_FLAG;

	if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)

		acc_dlc |= ACC_DLC_SSTX_FLAG;



	if (cf->can_id & CAN_EFF_FLAG) {

		acc_id = cf->can_id & CAN_EFF_MASK;

drivers/net/can/esd/esdacc.h

+20 −18
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ 
 */

#define ACC_OV_REG_FEAT_MASK_CANFD BIT(27 - 16)

#define ACC_OV_REG_FEAT_MASK_NEW_PSC BIT(28 - 16)

#define ACC_OV_REG_FEAT_MASK_DAR BIT(30 - 16)



#define ACC_OV_REG_MODE_MASK_ENDIAN_LITTLE BIT(0)

#define ACC_OV_REG_MODE_MASK_BM_ENABLE BIT(1)
@@ -50,7 +51,7 @@ 
#define ACC_OV_REG_MODE_MASK_FPGA_RESET BIT(31)



/* esdACC CAN Core Module */

#define ACC_CORE_OF_CTRL_MODE 0x0000

#define ACC_CORE_OF_CTRL 0x0000

#define ACC_CORE_OF_STATUS_IRQ 0x0008

#define ACC_CORE_OF_BRP	0x000c

#define ACC_CORE_OF_BTR	0x0010
@@ -66,21 +67,22 @@ 
#define ACC_CORE_OF_TXFIFO_DATA_0 0x00c8

#define ACC_CORE_OF_TXFIFO_DATA_1 0x00cc



#define ACC_REG_CONTROL_MASK_MODE_RESETMODE BIT(0)

#define ACC_REG_CONTROL_MASK_MODE_LOM BIT(1)

#define ACC_REG_CONTROL_MASK_MODE_STM BIT(2)

#define ACC_REG_CONTROL_MASK_MODE_TRANSEN BIT(5)

#define ACC_REG_CONTROL_MASK_MODE_TS BIT(6)

#define ACC_REG_CONTROL_MASK_MODE_SCHEDULE BIT(7)



#define ACC_REG_CONTROL_MASK_IE_RXTX BIT(8)

#define ACC_REG_CONTROL_MASK_IE_TXERROR BIT(9)

#define ACC_REG_CONTROL_MASK_IE_ERRWARN BIT(10)

#define ACC_REG_CONTROL_MASK_IE_OVERRUN BIT(11)

#define ACC_REG_CONTROL_MASK_IE_TSI BIT(12)

#define ACC_REG_CONTROL_MASK_IE_ERRPASS BIT(13)

#define ACC_REG_CONTROL_MASK_IE_ALI BIT(14)

#define ACC_REG_CONTROL_MASK_IE_BUSERR BIT(15)

/* CTRL register layout */

#define ACC_REG_CTRL_MASK_RESETMODE BIT(0)

#define ACC_REG_CTRL_MASK_LOM BIT(1)

#define ACC_REG_CTRL_MASK_STM BIT(2)

#define ACC_REG_CTRL_MASK_TRANSEN BIT(5)

#define ACC_REG_CTRL_MASK_TS BIT(6)

#define ACC_REG_CTRL_MASK_SCHEDULE BIT(7)



#define ACC_REG_CTRL_MASK_IE_RXTX BIT(8)

#define ACC_REG_CTRL_MASK_IE_TXERROR BIT(9)

#define ACC_REG_CTRL_MASK_IE_ERRWARN BIT(10)

#define ACC_REG_CTRL_MASK_IE_OVERRUN BIT(11)

#define ACC_REG_CTRL_MASK_IE_TSI BIT(12)

#define ACC_REG_CTRL_MASK_IE_ERRPASS BIT(13)

#define ACC_REG_CTRL_MASK_IE_ALI BIT(14)

#define ACC_REG_CTRL_MASK_IE_BUSERR BIT(15)



/* BRP and BTR register layout for CAN-Classic version */

#define ACC_REG_BRP_CL_MASK_BRP GENMASK(8, 0)
@@ -300,9 +302,9 @@ static inline void acc_clear_bits(struct acc_core *core, 


static inline int acc_resetmode_entered(struct acc_core *core)

{

	u32 ctrl = acc_read32(core, ACC_CORE_OF_CTRL_MODE);

	u32 ctrl = acc_read32(core, ACC_CORE_OF_CTRL);



	return (ctrl & ACC_REG_CONTROL_MASK_MODE_RESETMODE) != 0;

	return (ctrl & ACC_REG_CTRL_MASK_RESETMODE) != 0;

}



static inline u32 acc_ov_read32(struct acc_ov *ov, unsigned short offs)

drivers/net/can/flexcan/flexcan-core.c

+43 −7
Original line number Diff line number Diff line
@@ -354,6 +354,14 @@ static struct flexcan_devtype_data fsl_imx93_devtype_data = { 
		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,

};



static const struct flexcan_devtype_data fsl_imx95_devtype_data = {

	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |

		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |

		FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_FD |

		FLEXCAN_QUIRK_SUPPORT_ECC | FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |

		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR | FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI,

};



static const struct flexcan_devtype_data fsl_vf610_devtype_data = {

	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |

		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
@@ -544,6 +552,13 @@ static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv) 
	} else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR) {

		regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,

				   1 << priv->stm.req_bit, 1 << priv->stm.req_bit);

	} else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI) {

		/* For the SCMI mode, driver do nothing, ATF will send request to

		 * SM(system manager, M33 core) through SCMI protocol after linux

		 * suspend. Once SM get this request, it will send IPG_STOP signal

		 * to Flex_CAN, let CAN in STOP mode.

		 */

		return 0;

	}



	return flexcan_low_power_enter_ack(priv);
@@ -555,7 +570,11 @@ static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv) 
	u32 reg_mcr;

	int ret;



	/* remove stop request */

	/* Remove stop request, for FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI,

	 * do nothing here, because ATF already send request to SM before

	 * linux resume. Once SM get this request, it will deassert the

	 * IPG_STOP signal to Flex_CAN.

	 */

	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {

		ret = flexcan_stop_mode_enable_scfw(priv, false);

		if (ret < 0)
@@ -1983,6 +2002,9 @@ static int flexcan_setup_stop_mode(struct platform_device *pdev) 
		ret = flexcan_setup_stop_mode_scfw(pdev);

	else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR)

		ret = flexcan_setup_stop_mode_gpr(pdev);

	else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI)

		/* ATF will handle all STOP_IPG related work */

		ret = 0;

	else

		/* return 0 directly if doesn't support stop mode feature */

		return 0;
@@ -2009,6 +2031,7 @@ static const struct of_device_id flexcan_of_match[] = { 
	{ .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, },

	{ .compatible = "fsl,imx8mp-flexcan", .data = &fsl_imx8mp_devtype_data, },

	{ .compatible = "fsl,imx93-flexcan", .data = &fsl_imx93_devtype_data, },

	{ .compatible = "fsl,imx95-flexcan", .data = &fsl_imx95_devtype_data, },

	{ .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },

	{ .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },

	{ .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
@@ -2309,10 +2332,20 @@ static int __maybe_unused flexcan_noirq_suspend(struct device *device) 
		if (device_may_wakeup(device))

			flexcan_enable_wakeup_irq(priv, true);



		/* For FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI, it need ATF to send

		 * to SM through SCMI protocol, SM will assert the IPG_STOP

		 * signal. But all this works need the CAN clocks keep on.

		 * After the CAN module get the IPG_STOP mode, and switch to

		 * STOP mode, whether still keep the CAN clocks on or gate them

		 * off depend on the Hardware design.

		 */

		if (!(device_may_wakeup(device) &&

		      priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI)) {

			err = pm_runtime_force_suspend(device);

			if (err)

				return err;

		}

	}



	return 0;

}
@@ -2325,9 +2358,12 @@ static int __maybe_unused flexcan_noirq_resume(struct device *device) 
	if (netif_running(dev)) {

		int err;



		if (!(device_may_wakeup(device) &&

		      priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI)) {

			err = pm_runtime_force_resume(device);

			if (err)

				return err;

		}



		if (device_may_wakeup(device))

			flexcan_enable_wakeup_irq(priv, false);