Commit 2c4553e6 authored by Satya Priya Kakitapalli's avatar Satya Priya Kakitapalli Committed by Bjorn Andersson
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clk: qcom: clk-alpha-pll: Fix the pll post div mask 



The PLL_POST_DIV_MASK should be 0 to (width - 1) bits. Fix it.

Fixes: 1c354114 ("clk: qcom: support for 2 bit PLL post divider")
Cc: stable@vger.kernel.org
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarSatya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240731062916.2680823-2-quic_skakitap@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 8400291e

drivers/clk/qcom/clk-alpha-pll.c

+1 −1
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ 


#define PLL_USER_CTL(p)		((p)->offset + (p)->regs[PLL_OFF_USER_CTL])

# define PLL_POST_DIV_SHIFT	8

# define PLL_POST_DIV_MASK(p)	GENMASK((p)->width, 0)

# define PLL_POST_DIV_MASK(p)	GENMASK((p)->width - 1, 0)

# define PLL_ALPHA_EN		BIT(24)

# define PLL_ALPHA_MODE		BIT(25)

# define PLL_VCO_SHIFT		20