Commit 2c8ad2d5 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amd/display: Enable DCE12 support 



This wires DCE12 support into DC and enables it.

Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b8fdfcc6

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+4 −0
Original line number Diff line number Diff line
@@ -1984,8 +1984,12 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) 
	case CHIP_STONEY:

	case CHIP_POLARIS11:

	case CHIP_POLARIS10:

	case CHIP_POLARIS12:

	case CHIP_TONGA:

	case CHIP_FIJI:

#if defined(CONFIG_DRM_AMD_DC_DCE12_0)

	case CHIP_VEGA10:

#endif

#if defined(CONFIG_DRM_AMD_DC_PRE_VEGA)

		return amdgpu_dc != 0;

#else

drivers/gpu/drm/amd/display/Kconfig

+7 −0
Original line number Diff line number Diff line
@@ -17,6 +17,13 @@ config DRM_AMD_DC_PRE_VEGA 
	  by default. This includes Polaris, Carrizo, Tonga, Bonaire,

	  and Hawaii.



config DRM_AMD_DC_DCE12_0

        bool "Vega10 family"

        depends on DRM_AMD_DC

        help

         Choose this option if you want to have

         VG family for display engine.



config DEBUG_KERNEL_DC

	bool "Enable kgdb break in DC"

	depends on DRM_AMD_DC

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+19 −4
Original line number Diff line number Diff line
@@ -888,6 +888,10 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) 
	struct dc_interrupt_params int_params = {0};

	int r;

	int i;

	unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;



	if (adev->asic_type == CHIP_VEGA10)

		client_id = AMDGPU_IH_CLIENTID_DCE;



	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;

	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
@@ -904,7 +908,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) 


	/* Use VBLANK interrupt */

	for (i = 1; i <= adev->mode_info.num_crtc; i++) {

		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->crtc_irq);

		r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);



		if (r) {

			DRM_ERROR("Failed to add crtc irq id!\n");
@@ -927,7 +931,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) 
	/* Use GRPH_PFLIP interrupt */

	for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;

			i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {

		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);

		r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);

		if (r) {

			DRM_ERROR("Failed to add page flip irq id!\n");

			return r;
@@ -948,8 +952,8 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) 
	}



	/* HPD */

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A,

			&adev->hpd_irq);

	r = amdgpu_irq_add_id(adev, client_id,

			VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);

	if (r) {

		DRM_ERROR("Failed to add hpd irq id!\n");

		return r;
@@ -1119,6 +1123,9 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 
	case CHIP_POLARIS11:

	case CHIP_POLARIS10:

	case CHIP_POLARIS12:

#if defined(CONFIG_DRM_AMD_DC_DCE12_0)

	case CHIP_VEGA10:

#endif

		if (dce110_register_irq_handlers(dm->adev)) {

			DRM_ERROR("DM: Failed to initialize IRQ\n");

			return -1;
@@ -1312,6 +1319,7 @@ static const struct amdgpu_display_funcs dm_display_funcs = { 


};





#if defined(CONFIG_DEBUG_KERNEL_DC)



static ssize_t s3_debug_store(
@@ -1384,6 +1392,13 @@ static int dm_early_init(void *handle) 
		adev->mode_info.num_hpd = 6;

		adev->mode_info.num_dig = 6;

		break;

#if defined(CONFIG_DRM_AMD_DC_DCE12_0)

	case CHIP_VEGA10:

		adev->mode_info.num_crtc = 6;

		adev->mode_info.num_hpd = 6;

		adev->mode_info.num_dig = 6;

		break;

#endif

	default:

		DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);

		return -EINVAL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c

+10 −0
Original line number Diff line number Diff line
@@ -402,6 +402,16 @@ bool dm_pp_notify_wm_clock_changes( 
	return false;

}



#if defined(CONFIG_DRM_AMD_DC_DCE12_0)

bool dm_pp_notify_wm_clock_changes_soc15(

	const struct dc_context *ctx,

	struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)

{

	/* TODO: to be implemented */

	return false;

}

#endif



bool dm_pp_apply_power_level_change_request(

	const struct dc_context *ctx,

	struct dm_pp_power_level_change_request *level_change_req)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c

+21 −1
Original line number Diff line number Diff line
@@ -494,7 +494,7 @@ static void fill_plane_attributes_from_fb( 


	memset(&surface->tiling_info, 0, sizeof(surface->tiling_info));



	/* Fill GFX8 params */

	/* Fill GFX params */

	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1)

	{

		unsigned bankw, bankh, mtaspect, tile_split, num_banks;
@@ -523,6 +523,26 @@ static void fill_plane_attributes_from_fb( 
	surface->tiling_info.gfx8.pipe_config =

			AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);



#if defined (CONFIG_DRM_AMD_DC_DCE12_0)

	if (adev->asic_type == CHIP_VEGA10) {

		/* Fill GFX9 params */

		surface->tiling_info.gfx9.num_pipes =

			adev->gfx.config.gb_addr_config_fields.num_pipes;

		surface->tiling_info.gfx9.num_banks =

			adev->gfx.config.gb_addr_config_fields.num_banks;

		surface->tiling_info.gfx9.pipe_interleave =

			adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;

		surface->tiling_info.gfx9.num_shader_engines =

			adev->gfx.config.gb_addr_config_fields.num_se;

		surface->tiling_info.gfx9.max_compressed_frags =

			adev->gfx.config.gb_addr_config_fields.max_compress_frags;

		surface->tiling_info.gfx9.swizzle =

			AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);

		surface->tiling_info.gfx9.shaderEnable = 1;

	}

#endif





	surface->plane_size.grph.surface_size.x = 0;

	surface->plane_size.grph.surface_size.y = 0;

	surface->plane_size.grph.surface_size.width = fb->width;