Commit 2d0f973b authored by Bartosz Wawrzyniak's avatar Bartosz Wawrzyniak Committed by Vinod Koul
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phy: cadence: Sierra: Fix offset of DEQ open eye algorithm control register 



Fix the value of SIERRA_DEQ_OPENEYE_CTRL_PREG and add a definition for
SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG. This fixes the SGMII single link
register configuration.

Fixes: 7a5ad9b4 ("phy: cadence: Sierra: Update single link PCIe register configuration")
Signed-off-by: default avatarBartosz Wawrzyniak <bwawrzyn@cisco.com>
Link: https://lore.kernel.org/r/20241003123405.1101157-1-bwawrzyn@cisco.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent cb4c7df5

drivers/phy/cadence/phy-cadence-sierra.c

+11 −10
Original line number Diff line number Diff line
@@ -174,8 +174,9 @@ 
#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG		0x150

#define SIERRA_DEQ_TAU_CTRL2_PREG			0x151

#define SIERRA_DEQ_TAU_CTRL3_PREG			0x152

#define SIERRA_DEQ_OPENEYE_CTRL_PREG			0x158

#define SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG		0x158

#define SIERRA_DEQ_CONCUR_EPIOFFSET_MODE_PREG		0x159

#define SIERRA_DEQ_OPENEYE_CTRL_PREG			0x15C

#define SIERRA_DEQ_PICTRL_PREG				0x161

#define SIERRA_CPICAL_TMRVAL_MODE1_PREG			0x170

#define SIERRA_CPICAL_TMRVAL_MODE0_PREG			0x171
@@ -1733,7 +1734,7 @@ static const struct cdns_reg_pairs ml_pcie_100_no_ssc_ln_regs[] = { 
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
@@ -1797,7 +1798,7 @@ static const struct cdns_reg_pairs ti_ml_pcie_100_no_ssc_ln_regs[] = { 
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
@@ -1874,7 +1875,7 @@ static const struct cdns_reg_pairs ml_pcie_100_int_ssc_ln_regs[] = { 
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
@@ -1941,7 +1942,7 @@ static const struct cdns_reg_pairs ti_ml_pcie_100_int_ssc_ln_regs[] = { 
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
@@ -2012,7 +2013,7 @@ static const struct cdns_reg_pairs ml_pcie_100_ext_ssc_ln_regs[] = { 
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
@@ -2079,7 +2080,7 @@ static const struct cdns_reg_pairs ti_ml_pcie_100_ext_ssc_ln_regs[] = { 
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
@@ -2140,7 +2141,7 @@ static const struct cdns_reg_pairs cdns_pcie_ln_regs_no_ssc[] = { 
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
@@ -2215,7 +2216,7 @@ static const struct cdns_reg_pairs cdns_pcie_ln_regs_int_ssc[] = { 
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
@@ -2284,7 +2285,7 @@ static const struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = { 
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},