Unverified Commit 2d147d77 authored by Cyan Yang's avatar Cyan Yang Committed by Palmer Dabbelt
Browse files

riscv: Add SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions 



Add SiFive vendor extension support to the kernel with the target of
"xsfvqmaccdod" and "xsfvqmaccqoq".

Signed-off-by: default avatarCyan Yang <cyan.yang@sifive.com>
Link: https://lore.kernel.org/r/20250418053239.4351-3-cyan.yang@sifive.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 0f733b5b

arch/riscv/Kconfig.vendor

+13 −0
Original line number Diff line number Diff line
@@ -16,6 +16,19 @@ config RISCV_ISA_VENDOR_EXT_ANDES 
	  If you don't know what to do here, say Y.

endmenu



menu "SiFive"

config RISCV_ISA_VENDOR_EXT_SIFIVE

	bool "SiFive vendor extension support"

	select RISCV_ISA_VENDOR_EXT

	default y

	help

	  Say N here if you want to disable all SiFive vendor extension

	  support. This will cause any SiFive vendor extensions that are

	  requested by hardware probing to be ignored.



	  If you don't know what to do here, say Y.

endmenu



menu "T-Head"

config RISCV_ISA_VENDOR_EXT_THEAD

	bool "T-Head vendor extension support"

arch/riscv/include/asm/vendor_extensions/sifive.h

0 → 100644
+14 −0
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/* SPDX-License-Identifier: GPL-2.0 */

#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_SIFIVE_H

#define _ASM_RISCV_VENDOR_EXTENSIONS_SIFIVE_H



#include <asm/vendor_extensions.h>



#include <linux/types.h>



#define RISCV_ISA_VENDOR_EXT_XSFVQMACCDOD		0

#define RISCV_ISA_VENDOR_EXT_XSFVQMACCQOQ		1



extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_sifive;



#endif

arch/riscv/kernel/vendor_extensions.c

+10 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
#include <asm/vendorid_list.h>

#include <asm/vendor_extensions.h>

#include <asm/vendor_extensions/andes.h>

#include <asm/vendor_extensions/sifive.h>

#include <asm/vendor_extensions/thead.h>



#include <linux/array_size.h>
@@ -15,6 +16,9 @@ struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_ext_list[] = { 
#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_ANDES

	&riscv_isa_vendor_ext_list_andes,

#endif

#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE

	&riscv_isa_vendor_ext_list_sifive,

#endif

#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD

	&riscv_isa_vendor_ext_list_thead,

#endif
@@ -45,6 +49,12 @@ bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsig 
		cpu_bmap = riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap;

		break;

	#endif

	#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE

	case SIFIVE_VENDOR_ID:

		bmap = &riscv_isa_vendor_ext_list_sifive.all_harts_isa_bitmap;

		cpu_bmap = riscv_isa_vendor_ext_list_sifive.per_hart_isa_bitmap;

		break;

	#endif

	#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD

	case THEAD_VENDOR_ID:

		bmap = &riscv_isa_vendor_ext_list_thead.all_harts_isa_bitmap;

arch/riscv/kernel/vendor_extensions/Makefile

+1 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only



obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES)	+= andes.o

obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE)	+= sifive.o

obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD)	+= thead.o

obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD)	+= thead_hwprobe.o

arch/riscv/kernel/vendor_extensions/sifive.c

0 → 100644
+19 −0
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// SPDX-License-Identifier: GPL-2.0-only



#include <asm/cpufeature.h>

#include <asm/vendor_extensions.h>

#include <asm/vendor_extensions/sifive.h>



#include <linux/array_size.h>

#include <linux/types.h>



/* All SiFive vendor extensions supported in Linux */

const struct riscv_isa_ext_data riscv_isa_vendor_ext_sifive[] = {

	__RISCV_ISA_EXT_DATA(xsfvqmaccdod, RISCV_ISA_VENDOR_EXT_XSFVQMACCDOD),

	__RISCV_ISA_EXT_DATA(xsfvqmaccqoq, RISCV_ISA_VENDOR_EXT_XSFVQMACCQOQ),

};



struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_sifive = {

	.ext_data_count = ARRAY_SIZE(riscv_isa_vendor_ext_sifive),

	.ext_data = riscv_isa_vendor_ext_sifive,

};