Commit 2d1ec1e9 authored by Mario Limonciello's avatar Mario Limonciello Committed by Alex Deucher
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drm/amd: Allow printing VanGogh OD SCLK levels without setting dpm to manual 



Several other ASICs allow printing OD SCLK levels without setting DPM
control to manual.  When OD is disabled it will show the range the
hardware supports. When OD is enabled it will show what values have
been programmed. Adjust VanGogh to work the same.

Cc: Pierre-Loup A. Griffais <pgriffais@valvesoftware.com>
Reported-by: default avatarVicki Pfau <vi@endrift.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Link: https://lore.kernel.org/r/20250609031227.479079-1-superm1@kernel.org


Signed-off-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d2f90024

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

+15 −22
Original line number Diff line number Diff line
@@ -666,7 +666,6 @@ static int vangogh_print_clk_levels(struct smu_context *smu, 
{

	DpmClocks_t *clk_table = smu->smu_table.clocks_table;

	SmuMetrics_t metrics;

	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);

	int i, idx, size = 0, ret = 0;

	uint32_t cur_value = 0, value = 0, count = 0;

	bool cur_value_match_level = false;
@@ -682,31 +681,25 @@ static int vangogh_print_clk_levels(struct smu_context *smu, 


	switch (clk_type) {

	case SMU_OD_SCLK:

		if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {

		size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");

		size += sysfs_emit_at(buf, size, "0: %10uMhz\n",

		(smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);

		size += sysfs_emit_at(buf, size, "1: %10uMhz\n",

		(smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);

		}

		break;

	case SMU_OD_CCLK:

		if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {

		size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n",  smu->cpu_core_id_select);

		size += sysfs_emit_at(buf, size, "0: %10uMhz\n",

		(smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);

		size += sysfs_emit_at(buf, size, "1: %10uMhz\n",

		(smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);

		}

		break;

	case SMU_OD_RANGE:

		if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {

		size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");

		size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",

			smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);

		size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",

			smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);

		}

		break;

	case SMU_SOCCLK:

		/* the level 3 ~ 6 of socclk use the same frequency for vangogh */