Commit 2d3b3ab8 authored Jan 19, 2024 by Radhey Shyam Pandey Committed by Rob Herring Jan 31, 2024

dt-bindings: xilinx: replace Piyush Mehta maintainership



As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO
controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed
DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and
Xilinx udc controller maintainership duties to Mubin and Radhey.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Acked-by: Mubin Sayyed <mubin.sayyed@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Piyush Mehta <piyush.mehta@amd.com>
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Acked-by: Niklas Cassel <cassel@kernel.org>
Link: https://lore.kernel.org/r/1705664181-722937-1-git-send-email-radhey.shyam.pandey@amd.com


Signed-off-by: Rob Herring <robh@kernel.org>

parent 6154fb9c

Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml

+2 −1

Original line number	Diff line number	Diff line
		@@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
		title: Ceva AHCI SATA Controller

		maintainers:
		- Piyush Mehta <piyush.mehta@amd.com>
		- Mubin Sayyed <mubin.sayyed@amd.com>
		- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>

		description: \|
		The Ceva SATA controller mostly conforms to the AHCI interface with some

Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml

+2 −1

Original line number	Diff line number	Diff line
		@@ -12,7 +12,8 @@ description:
		PS_MODE). Every pin can be configured as input/output.

		maintainers:
		- Piyush Mehta <piyush.mehta@amd.com>
		- Mubin Sayyed <mubin.sayyed@amd.com>
		- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>

		properties:
		compatible:

Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml

+2 −1

Original line number	Diff line number	Diff line
		@@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
		title: Zynq UltraScale+ MPSoC and Versal reset

		maintainers:
		- Piyush Mehta <piyush.mehta@amd.com>
		- Mubin Sayyed <mubin.sayyed@amd.com>
		- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>

		description: \|
		The Zynq UltraScale+ MPSoC and Versal has several different resets.

Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml

+2 −1

Original line number	Diff line number	Diff line
		@@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
		title: Xilinx SuperSpeed DWC3 USB SoC controller

		maintainers:
		- Piyush Mehta <piyush.mehta@amd.com>
		- Mubin Sayyed <mubin.sayyed@amd.com>
		- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>

		properties:
		compatible:

Documentation/devicetree/bindings/usb/microchip,usb5744.yaml

+2 −1

Original line number	Diff line number	Diff line
		@@ -16,8 +16,9 @@ description:
		USB 2.0 traffic.

		maintainers:
		- Piyush Mehta <piyush.mehta@amd.com>
		- Michal Simek <michal.simek@amd.com>
		- Mubin Sayyed <mubin.sayyed@amd.com>
		- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>

		properties:
		compatible: