Commit 2d539f31 authored by Raghav Sharma's avatar Raghav Sharma Committed by Krzysztof Kozlowski
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clk: samsung: exynosautov920: add block hsi2 clock support 



Register compatible and cmu_info data to support clocks.
CMU_HSI2, this provides clocks for HSI2 block

Signed-off-by: default avatarRaghav Sharma <raghav.s@samsung.com>
Reviewed-by: default avatarAlim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20250529112640.1646740-4-raghav.s@samsung.com


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 5324ed66

drivers/clk/samsung/clk-exynosautov920.c

+72 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
#define CLKS_NR_MISC			(CLK_DOUT_MISC_OSC_DIV2 + 1)

#define CLKS_NR_HSI0			(CLK_DOUT_HSI0_PCIE_APB + 1)

#define CLKS_NR_HSI1			(CLK_MOUT_HSI1_USBDRD + 1)

#define CLKS_NR_HSI2			(CLK_DOUT_HSI2_ETHERNET_PTP + 1)



/* ---- CMU_TOP ------------------------------------------------------------ */
@@ -1752,6 +1753,74 @@ static const struct samsung_cmu_info hsi1_cmu_info __initconst = { 
	.clk_name		= "noc",

};



/* ---- CMU_HSI2 --------------------------------------------------------- */



/* Register Offset definitions for CMU_HSI2 (0x16b00000) */

#define PLL_LOCKTIME_PLL_ETH                    0x0

#define PLL_CON3_PLL_ETH			0x10c

#define PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER  0x600

#define PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER   0x610

#define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER  0x630

#define CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET       0x1000

#define CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET       0x1800

#define CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP   0x1804



static const unsigned long hsi2_clk_regs[] __initconst = {

	PLL_LOCKTIME_PLL_ETH,

	PLL_CON3_PLL_ETH,

	PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER,

	PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER,

	PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER,

	CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET,

	CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET,

	CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP,

};



static const struct samsung_pll_clock hsi2_pll_clks[] __initconst = {

	/* CMU_HSI2_PLL */

	PLL(pll_531x, FOUT_PLL_ETH, "fout_pll_eth", "oscclk",

	    PLL_LOCKTIME_PLL_ETH, PLL_CON3_PLL_ETH, NULL),

};



/* List of parent clocks for Muxes in CMU_HSI2 */

PNAME(mout_clkcmu_hsi2_noc_ufs_user_p) = { "oscclk", "dout_clkcmu_hsi2_noc_ufs" };

PNAME(mout_clkcmu_hsi2_ufs_embd_user_p) = { "oscclk", "dout_clkcmu_hsi2_ufs_embd" };

PNAME(mout_hsi2_ethernet_p) = { "fout_pll_eth", "mout_clkcmu_hsi2_ethernet_user" };

PNAME(mout_clkcmu_hsi2_ethernet_user_p) = { "oscclk", "dout_clkcmu_hsi2_ethernet" };



static const struct samsung_mux_clock hsi2_mux_clks[] __initconst = {

	MUX(CLK_MOUT_HSI2_NOC_UFS_USER, "mout_clkcmu_hsi2_noc_ufs_user",

	    mout_clkcmu_hsi2_noc_ufs_user_p, PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER, 4, 1),

	MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_clkcmu_hsi2_ufs_embd_user",

	    mout_clkcmu_hsi2_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER, 4, 1),

	MUX(CLK_MOUT_HSI2_ETHERNET, "mout_hsi2_ethernet",

	    mout_hsi2_ethernet_p, CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET, 0, 1),

	MUX(CLK_MOUT_HSI2_ETHERNET_USER, "mout_clkcmu_hsi2_ethernet_user",

	    mout_clkcmu_hsi2_ethernet_user_p, PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER, 4, 1),

};



static const struct samsung_div_clock hsi2_div_clks[] __initconst = {

	DIV(CLK_DOUT_HSI2_ETHERNET, "dout_hsi2_ethernet",

	    "mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET,

	    0, 4),

	DIV(CLK_DOUT_HSI2_ETHERNET_PTP, "dout_hsi2_ethernet_ptp",

	    "mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP,

	    0, 4),

};



static const struct samsung_cmu_info hsi2_cmu_info __initconst = {

	.pll_clks               = hsi2_pll_clks,

	.nr_pll_clks            = ARRAY_SIZE(hsi2_pll_clks),

	.mux_clks               = hsi2_mux_clks,

	.nr_mux_clks            = ARRAY_SIZE(hsi2_mux_clks),

	.div_clks               = hsi2_div_clks,

	.nr_div_clks            = ARRAY_SIZE(hsi2_div_clks),

	.nr_clk_ids             = CLKS_NR_HSI2,

	.clk_regs               = hsi2_clk_regs,

	.nr_clk_regs            = ARRAY_SIZE(hsi2_clk_regs),

	.clk_name               = "noc",

};



static int __init exynosautov920_cmu_probe(struct platform_device *pdev)

{

	const struct samsung_cmu_info *info;
@@ -1779,6 +1848,9 @@ static const struct of_device_id exynosautov920_cmu_of_match[] = { 
	}, {

		.compatible = "samsung,exynosautov920-cmu-hsi1",

		.data = &hsi1_cmu_info,

	}, {

		.compatible = "samsung,exynosautov920-cmu-hsi2",

		.data = &hsi2_cmu_info,

	},

	{ }

};