Commit 2d6c7bcc authored by Neil Armstrong's avatar Neil Armstrong Committed by Martin K. Petersen
Browse files

scsi: ufs: core: Track when MCQ ESI is enabled 



In preparation of adding a threaded interrupt handler, track when the
MCQ ESI interrupt handlers were installed so we can optimize the MCQ
interrupt handling to avoid walking the threaded handler in the case ESI
handlers are enabled.

Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250407-topic-ufs-use-threaded-irq-v3-2-08bee980f71e@linaro.org


Reviewed-by: default avatarBart Van Assche <bvanassche@acm.org>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 56f4beff

drivers/ufs/core/ufshcd.c

+1 −0
Original line number Diff line number Diff line
@@ -8717,6 +8717,7 @@ static void ufshcd_config_mcq(struct ufs_hba *hba) 
	u32 intrs;



	ret = ufshcd_mcq_vops_config_esi(hba);

	hba->mcq_esi_enabled = !ret;

	dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : "");



	intrs = UFSHCD_ENABLE_MCQ_INTRS;

include/ufs/ufshcd.h

+2 −0
Original line number Diff line number Diff line
@@ -954,6 +954,7 @@ enum ufshcd_mcq_opr { 
 *	ufshcd_resume_complete()

 * @mcq_sup: is mcq supported by UFSHC

 * @mcq_enabled: is mcq ready to accept requests

 * @mcq_esi_enabled: is mcq ESI configured

 * @res: array of resource info of MCQ registers

 * @mcq_base: Multi circular queue registers base address

 * @uhq: array of supported hardware queues
@@ -1122,6 +1123,7 @@ struct ufs_hba { 
	bool mcq_sup;

	bool lsdb_sup;

	bool mcq_enabled;

	bool mcq_esi_enabled;

	struct ufshcd_res_info res[RES_MAX];

	void __iomem *mcq_base;

	struct ufs_hw_queue *uhq;